Custom IC Design

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Discussion

What is the difference between pmos, pmoshiv, pmos3, and pmostie in Cadence gpdk018?

Category: Custom IC Design

By SimbaG

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updated over 4 years ago by SimbaG

2 replies • 12392 views
Discussion

Netlisting flowchart postFunc called multiple times with Assembler & ICRP job control

Category: Custom IC Design

By smikes

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updated over 4 years ago by Andrew Beckett

1 replies • 1033 views
Discussion

Dynamic tolerance with Spectre X?

Category: Custom IC Design

By smikes

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updated over 4 years ago by Andrew Beckett

1 replies • 11986 views
Discussion

How to combine two procedure syntax and use by bindkey layer?

Category: Custom IC Design

By toyakoyosu

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updated over 4 years ago by Andrew Beckett

3 replies • 11118 views
Discussion

Controlling the displayed number of floating decimals in the DC operating point

Category: Custom IC Design

By Javier Beloso

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updated over 4 years ago by Javier Beloso

2 replies • 13429 views
Discussion

Setting for setting the analog stimuli

Category: Custom IC Design

By sidm

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updated over 4 years ago by sidm

4 replies • 14296 views
Discussion

How to move symbol origin for only SOME instances

Category: Custom IC Design

By Ahmed A Elsayed

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updated over 4 years ago by Ahmed A Elsayed

3 replies • 12135 views
Discussion

dynamic stop time in transient analysis

Category: Custom IC Design

By Hazem Al Indari

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updated over 4 years ago by Marc Heise

5 replies • 15132 views
Discussion

No such feature exists. error from lmutil lmdiag command

Category: Custom IC Design

By Layne Bunker

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updated over 4 years ago by Frank Wiedmann

2 replies • 12405 views
Discussion

DSPF cellview in Hierarchy Editor will be always netlisted with "subcircuit" model name

Category: Custom IC Design

By ZoltanT

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updated over 4 years ago by ZoltanT

7 replies • 5093 views
Discussion

Stretching multiple layout wires at once

Category: Custom IC Design

By hesaliveJim

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updated over 4 years ago by Andrew Beckett

4 replies • 13617 views
Discussion

Defining supply voltage (and basic connect rules) for digital block for runams

Category: Custom IC Design

By jehh

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updated over 4 years ago by jehh

2 replies • 12483 views
Discussion

Stop an area of a schematic being netlisted.

Category: Custom IC Design

By FAwqati

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updated over 4 years ago by FAwqati

4 replies • 11561 views
Discussion

Does PNOISE sim of a sample & hold circuit include clock jitter effect?

Category: Custom IC Design

By peter6g

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updated over 4 years ago by Andrew Beckett

6 replies • 5496 views
Discussion

How to exploit annotation browser connectivity for custom cells?

Category: Custom IC Design

By YJ Jo

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updated over 4 years ago by Andrew Beckett

5 replies • 11705 views

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