Custom IC Design

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Discussion

I cannot open maestro or adexl views (IC 6.1.8)

Category: Custom IC Design

By MA202408239313

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started 3 months ago

0 replies • 1127 views
Discussion

How to turn off filter and Pass/Fail column at the results window (semi-)permanently?

Category: Custom IC Design

By kolep

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updated 3 months ago by Andrew Beckett

1 replies • 410 views
Discussion

viva env variable to control the trace name in the legend

Category: Custom IC Design

By kolep

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updated 3 months ago by Andrew Beckett

6 replies • 1489 views
Discussion

Issue with Skywater 130 Monte Carlo Mismatch Analysis

Category: Custom IC Design

By VLSI lab IITB

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updated 3 months ago by Andrew Beckett

6 replies • 2661 views
Discussion

gpdk045 (sram) memory compiler?

Category: Custom IC Design

By GS202507021424

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started 3 months ago

0 replies • 1109 views
Discussion

Imported newly created calcVal expressions from csv file into outputs results in "eval error"

Category: Custom IC Design

By rod1

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updated 3 months ago by rod1

1 replies • 441 views
Discussion

Offset Parameters in Instance Array

Category: Custom IC Design

By AR202511272845

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updated 3 months ago by Andrew Beckett

1 replies • 1062 views
Discussion

Stream out/LVS Error occurs with PCELL which is made by Skill Script and CDF Parameters

Category: Custom IC Design

By KO20251123107

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updated 3 months ago by KO20251123107

2 replies • 740 views
Discussion

ERROR (USIMUWI-20005)

Category: Custom IC Design

By TUKA

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updated 3 months ago by TUKA

2 replies • 1177 views
Discussion

Register Host ID

Category: Custom IC Design

By SM202508046750

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updated 3 months ago by Andrew Beckett

1 replies • 1111 views
Discussion

PSS + PSTB for Buck converter

Category: Custom IC Design

By TH202510293247

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updated 3 months ago by Frank Wiedmann

17 replies • 4591 views
Discussion

*Error* lookup: Given symbol name is longer than 255 characters

Category: Custom IC Design

By ajk68

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started 3 months ago

0 replies • 1178 views
Discussion

skill debugging in CIW (6.1.7)

Category: Custom IC Design

By JJ202502261359

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updated 3 months ago by Andrew Beckett

1 replies • 1381 views
Discussion

Methodology for Sweeping Vth (delvto) or Defining Sigma Corners for DAC Mismatch Analysis?

Category: Custom IC Design

By VP202511202051

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updated 3 months ago by VP202511202051

1 replies • 1288 views
Discussion

Exceeded the blowup limit when running Monte Carlo analysis

Category: Custom IC Design

By aalbason

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updated 3 months ago by aalbason

3 replies • 1601 views

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