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Custom IC Design

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  • Discussion

    xmax and xmin are returning nil

    Category: Custom IC Design

    By asetji

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    updated over 8 years ago by asetji

    2 replies • 15807 views
  • Discussion

    How can I use a vpwlf source with design variable for filename in AMS simulator (with UNL)?

    Category: Custom IC Design

    By mad monster

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    updated over 8 years ago by mad monster

    1 replies • 7134 views
  • Discussion

    Printing Corner Analysis information using VerilogA module

    Category: Custom IC Design

    By ashrafSazid

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    started over 8 years ago

    0 replies • 13496 views
  • Discussion

    Hierarchy Editor: Instance bindings @ 2nd level of hierarchy depth

    Category: Custom IC Design

    By PNadeau

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    •

    updated over 8 years ago by PNadeau

    2 replies • 15701 views
  • Discussion

    Automatic naming of ADEXL history items

    Category: Custom IC Design

    By PNadeau

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    •

    started over 8 years ago

    0 replies • 14709 views
  • Discussion

    MATLAB crashing with SpectreRF Toolbox

    Category: Custom IC Design

    By doorscops

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    updated over 8 years ago by lekez2005

    5 replies • 15926 views
  • Discussion

    [URI] Issues usign the scaleparam function in the URI (Unified Reliability Interface) with multiple aging models.

    Category: Custom IC Design

    By FAVG

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    updated over 8 years ago by Andrew Beckett

    1 replies • 14561 views
  • Discussion

    Reg channel length in gpdk045

    Category: Custom IC Design

    By Pasupathy KR

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    •

    started over 8 years ago

    0 replies • 14044 views
  • Discussion

    Modifying extracted netlist for post layout simulation

    Category: Custom IC Design

    By Hasan91

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    •

    started over 8 years ago

    0 replies • 14198 views
  • Discussion

    Problem in QRC Extraction due to inconsistent models

    Category: Custom IC Design

    By Casp

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    •

    updated over 8 years ago by DeepAG

    3 replies • 14465 views
  • Discussion

    Floorplanner generate physical hierarchy

    Category: Custom IC Design

    By RVERP

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    •

    started over 8 years ago

    0 replies • 13942 views
  • Discussion

    [ADE XL] Compiling verilog-A module

    Category: Custom IC Design

    By Seokhyun Jeong

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    •

    started over 8 years ago

    0 replies • 14581 views
  • Discussion

    Layout XL: how to set default options for Selection Protection?

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 8 years ago by dontpanic

    4 replies • 17002 views
  • Discussion

    How to subtract a wire/path from a polygon

    Category: Custom IC Design

    By JWHoll

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 3983 views
  • Discussion

    QRC (EXT91) always fails

    Category: Custom IC Design

    By Zach

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    •

    updated over 8 years ago by Quek

    6 replies • 17774 views
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