Custom IC Design

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Maestro: Simulation Settings as Output Expressions

Category: Custom IC Design

By Saikiran IND

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updated over 2 years ago by Saikiran IND

2 replies • 6815 views
Discussion

The region of operation of MOS transistor

Category: Custom IC Design

By PhD Student

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updated over 2 years ago by PhD Student

12 replies • 13518 views
Discussion

Simulation startup is too slow

Category: Custom IC Design

By Firdos

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updated over 2 years ago by ShawnLogan

1 replies • 6578 views
Discussion

rexMatchp error when netlist

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by Andrew Beckett

1 replies • 6604 views
Discussion

Ramp signal generator in Verilog-A

Category: Custom IC Design

By delgsy

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updated over 2 years ago by ShawnLogan

1 replies • 9329 views
Discussion

Post Trimming Simulation for Oscillator Circuit

Category: Custom IC Design

By yoshi777

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updated over 2 years ago by ShawnLogan

8 replies • 10583 views
Discussion

design/global variables import from veilogA

Category: Custom IC Design

By Majco

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started over 2 years ago

0 replies • 823 views
Discussion

Pixelate Custom Curved Polygon According to Grid in Virtuoso Layout Suite L

Category: Custom IC Design

By Herramar

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updated over 2 years ago by Andrew Beckett

3 replies • 7145 views
Discussion

Unexpected capacitor values in the av_extracted view file output?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Vishesh Gupta

6 replies • 8002 views
Discussion

How to compare the before and after extraction values of resistance and capacitance?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Vishesh Gupta

8 replies • 8139 views
Discussion

Title Block cell issue

Category: Custom IC Design

By Larry Allen

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updated over 2 years ago by Andrew Beckett

6 replies • 7102 views
Discussion

Importance of "Enable CellView Check" while filling the quantus assura extraction form?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Vishesh Gupta

2 replies • 1277 views
Discussion

sum of sampled_noise output spectrum, how to access the phase information?

Category: Custom IC Design

By NewScreenName

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updated over 2 years ago by NewScreenName

14 replies • 9487 views
Discussion

ERROR: ADE-5014 in ams simulation

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by sjwprcker

2 replies • 7034 views
Discussion

How to include extracted output in your adexl simulation?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Vishesh Gupta

6 replies • 8137 views

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