Custom IC Design

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Discussion

Integrated noise for opamp is not converged.

Category: Custom IC Design

By Jacki

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updated over 13 years ago by samiic

10 replies • 16897 views
Discussion

Problems during ADE simulation

Category: Custom IC Design

By erangle

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updated over 13 years ago by tkhan

5 replies • 14333 views
Discussion

Problems importing a CDL with resistors and diodes

Category: Custom IC Design

By TAnderson

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updated over 13 years ago by TAnderson

3 replies • 14576 views
Discussion

Checking error status after SKILL function execution.

Category: Custom IC Design

By Runner

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updated over 13 years ago by Andrew Beckett

1 replies • 13022 views
Discussion

how to find out gate capacitance

Category: Custom IC Design

By cupidsd

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updated over 13 years ago by baenischfau

1 replies • 15020 views
Discussion

Transient Analysis: tran_info and finalTimeOP

Category: Custom IC Design

By BVT1

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started over 13 years ago

0 replies • 13325 views
Discussion

verilog-a - model ac biasing

Category: Custom IC Design

By soathana

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updated over 13 years ago by ESTEC

4 replies • 1877 views
Discussion

Can't import techfile into abstract (IC6.1.4)

Category: Custom IC Design

By dura

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updated over 13 years ago by Aritra

2 replies • 1088 views
Discussion

Translating IC5 libaries to IC6

Category: Custom IC Design

By DineshBabu

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updated over 13 years ago by DineshBabu

2 replies • 15964 views
Discussion

how to recover a locked simulation on the Cadence server?

Category: Custom IC Design

By sohaibafridi

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updated over 13 years ago by Quek

11 replies • 6428 views
Discussion

getting rid of little informational text on mpps

Category: Custom IC Design

By linbo

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updated over 13 years ago by linbo

3 replies • 13569 views
Discussion

Writing simulation data into a file after running

Category: Custom IC Design

By Medya

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updated over 13 years ago by Andrew Beckett

1 replies • 13141 views
Discussion

ADE XL: default x axis for plots

Category: Custom IC Design

By keble6

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updated over 13 years ago by keble6

2 replies • 13970 views
Discussion

Parameterized VHDL using generics and ADE-AMS simulation

Category: Custom IC Design

By lperktold

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started over 13 years ago

0 replies • 13494 views
Discussion

get first pole from PZ analysis

Category: Custom IC Design

By Rainer123

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updated over 13 years ago by Rainer123

4 replies • 13811 views

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