Custom IC Design

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Discussion

Device Checking, how to exclude one sub-circuit

Category: Custom IC Design

By Derek WANG

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updated over 10 years ago by Andrew Beckett

1 replies • 13600 views
Discussion

How to interpret (monte carlo simulation)?

Category: Custom IC Design

By pitter

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updated over 10 years ago by Andrew Beckett

5 replies • 14354 views
Discussion

cdsServIpc - ERROR (cmms-1889): Unknown switch '-c'

Category: Custom IC Design

By Karzo

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updated over 10 years ago by Andrew Beckett

1 replies • 2641 views
Discussion

Problem with importing verilog to Cadence virtuoso

Category: Custom IC Design

By aamn

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updated over 10 years ago by Andrew Beckett

2 replies • 14874 views
Discussion

Can I use a "not synthesized verilog file" in Cadence Virtuoso?

Category: Custom IC Design

By aamn

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updated over 10 years ago by Andrew Beckett

1 replies • 1075 views
Discussion

How to perform a DOE (Design of Experiment) in Cadence?

Category: Custom IC Design

By Pyroblast

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updated over 10 years ago by Andrew Beckett

2 replies • 13628 views
Discussion

Virtuoso AnalogEnvironment : netlisting without ocean

Category: Custom IC Design

By samung

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updated over 10 years ago by Andrew Beckett

1 replies • 13034 views
Discussion

Monte-Carlo simulation finish anormally

Category: Custom IC Design

By UUinfini

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updated over 10 years ago by Andrew Beckett

1 replies • 12944 views
Discussion

Batch run of ADE simulations using skill

Category: Custom IC Design

By pshan

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started over 10 years ago

0 replies • 13560 views
Discussion

Reliability study: Spectre vs Relxpert

Category: Custom IC Design

By Gurunath Kadam

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updated over 10 years ago by Gurunath Kadam

1 replies • 14492 views
Discussion

Layout XL: "Connectivity->Update->Components and Nets" resets all my pins

Category: Custom IC Design

By PNadeau

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updated over 10 years ago by PNadeau

7 replies • 9098 views
Discussion

Ultrasim: individual accuracy setting on subcircuit level ?

Category: Custom IC Design

By baenischfau

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updated over 10 years ago by PNadeau

6 replies • 16790 views
Discussion

Changing config view within a single ADEXL test

Category: Custom IC Design

By Ivars

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updated over 10 years ago by Tom Volden

4 replies • 18476 views
Discussion

Instantiating Spectre/Spice module inside Systemverilog testbench for irun based flow

Category: Custom IC Design

By rrpat

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updated over 10 years ago by rrpat

1 replies • 1547 views
Discussion

Design of Inductor in CMOS - Help needed

Category: Custom IC Design

By Pyroblast

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updated over 10 years ago by Andrew Beckett

3 replies • 1954 views

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