Custom IC Design

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Discussion

Mismatch and Process Spread data in Monte Carlo simulations

Category: Custom IC Design

By Flyyn Rider

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updated over 11 years ago by Flyyn Rider

4 replies • 15565 views
Discussion

Error in delay calculation

Category: Custom IC Design

By KISHORE085

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updated over 11 years ago by frankaurora

5 replies • 16045 views
Discussion

passing CDF parameters to verilog block in SpectreVerilog simulations

Category: Custom IC Design

By RomeshNandwana

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updated over 11 years ago by RomeshNandwana

5 replies • 16305 views
Discussion

Switched Capacitor Bandgap Reference LVS Issue

Category: Custom IC Design

By Jake98

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updated over 11 years ago by Jake98

3 replies • 13906 views
Discussion

Is the device capacitance bias-dependent or independent?

Category: Custom IC Design

By Alex Liao

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updated over 11 years ago by Alex Liao

6 replies • 15608 views
Discussion

monte-carlo simulation running one seed

Category: Custom IC Design

By frogconsultant

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updated over 11 years ago by Frank Wiedmann

12 replies • 26013 views
Discussion

HELP!!! insert gpdk180 into IC615

Category: Custom IC Design

By hTmTech

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updated over 11 years ago by hTmTech

7 replies • 22878 views
Discussion

ADE XL - Message 1612

Category: Custom IC Design

By shayM

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updated over 11 years ago by shayM

2 replies • 2003 views
Discussion

Creating a user defined Voltage source

Category: Custom IC Design

By Debajit B

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updated over 11 years ago by Debajit B

3 replies • 14756 views
Discussion

ocnxlRun never returns as some splits are hung forever

Category: Custom IC Design

By Tajinder

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updated over 11 years ago by Tajinder

3 replies • 13463 views
Discussion

SpiceIn - how to map to a total width from w and m in the CDL

Category: Custom IC Design

By WMACH

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updated over 11 years ago by skillUser

4 replies • 4652 views
Discussion

" *Error* plus: can't handle (nil + nil) " during netlisting in icfb

Category: Custom IC Design

By yayla

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updated over 11 years ago by shila sh

7 replies • 14581 views
Discussion

AMS simulation taking very small step sizes. Help in finding offending connect modules?

Category: Custom IC Design

By Amblikai

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started over 11 years ago

0 replies • 13273 views
Discussion

Issue with DRC - "run is invalid"

Category: Custom IC Design

By apaj

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updated over 11 years ago by Quek

10 replies • 4531 views
Discussion

Extracting generic devices with Assura

Category: Custom IC Design

By PietroUser

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updated over 11 years ago by Andrew Beckett

3 replies • 13625 views

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