Custom IC Design

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Discussion

how to find out gate capacitance

Category: Custom IC Design

By cupidsd

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updated over 13 years ago by baenischfau

1 replies • 14999 views
Discussion

Transient Analysis: tran_info and finalTimeOP

Category: Custom IC Design

By BVT1

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started over 13 years ago

0 replies • 13305 views
Discussion

verilog-a - model ac biasing

Category: Custom IC Design

By soathana

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updated over 13 years ago by ESTEC

4 replies • 1869 views
Discussion

Can't import techfile into abstract (IC6.1.4)

Category: Custom IC Design

By dura

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updated over 13 years ago by Aritra

2 replies • 1084 views
Discussion

Translating IC5 libaries to IC6

Category: Custom IC Design

By DineshBabu

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updated over 13 years ago by DineshBabu

2 replies • 15944 views
Discussion

how to recover a locked simulation on the Cadence server?

Category: Custom IC Design

By sohaibafridi

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updated over 13 years ago by Quek

11 replies • 6406 views
Discussion

getting rid of little informational text on mpps

Category: Custom IC Design

By linbo

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updated over 13 years ago by linbo

3 replies • 13547 views
Discussion

Writing simulation data into a file after running

Category: Custom IC Design

By Medya

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updated over 13 years ago by Andrew Beckett

1 replies • 13122 views
Discussion

ADE XL: default x axis for plots

Category: Custom IC Design

By keble6

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updated over 13 years ago by keble6

2 replies • 13945 views
Discussion

Parameterized VHDL using generics and ADE-AMS simulation

Category: Custom IC Design

By lperktold

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started over 13 years ago

0 replies • 13473 views
Discussion

get first pole from PZ analysis

Category: Custom IC Design

By Rainer123

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updated over 13 years ago by Rainer123

4 replies • 13785 views
Discussion

Generate Clones does not work

Category: Custom IC Design

By tyanata

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updated over 13 years ago by tyanata

2 replies • 14025 views
Discussion

DC Match Over Corners

Category: Custom IC Design

By BVT1

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started over 13 years ago

0 replies • 13228 views
Discussion

How to translate netlist with subcircuits into top-level subcircuit?

Category: Custom IC Design

By TiNat

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updated over 13 years ago by skillUser

1 replies • 6466 views
Discussion

Assura LVS error (cell expanded), need help debugging the error !!

Category: Custom IC Design

By SivaChaitanya

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updated over 13 years ago by SivaChaitanya

1 replies • 16851 views

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