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Custom IC Design

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  • Discussion

    maestro' test name not updated

    Category: Custom IC Design

    By dogman4

    •

    updated over 1 year ago by dogman4

    4 replies • 1481 views
  • Discussion

    python script which can connect with virtuoso

    Category: Custom IC Design

    By AG20250626213

    •

    started over 1 year ago

    0 replies • 2407 views
  • Discussion

    Probing current of an instance using hidden supply pins

    Category: Custom IC Design

    By Volker T

    •

    updated over 1 year ago by Volker T

    1 replies • 3017 views
  • Discussion

    How to prevent parameter updates for pending simulations during ADEXL simulation

    Category: Custom IC Design

    By dogman4

    •

    updated over 1 year ago by dogman4

    10 replies • 5482 views
  • Discussion

    adexl's "Run Simulation" always hidden when first open

    Category: Custom IC Design

    By dogman4

    •

    updated over 1 year ago by dogman4

    3 replies • 1138 views
  • Discussion

    Function to Detect Minimum Pulse Width

    Category: Custom IC Design

    By Kevin T Buck

    •

    updated over 1 year ago by Kevin T Buck

    1 replies • 2923 views
  • Discussion

    Problem with Liberate and Verilog-A Model

    Category: Custom IC Design

    By FM202408077836

    •

    updated over 1 year ago by FM202408077836

    2 replies • 4756 views
  • Discussion

    Layout: Edit-in Place -> show full layer palette

    Category: Custom IC Design

    By PK202501238151

    •

    updated over 1 year ago by PK202501238151

    2 replies • 1401 views
  • Discussion

    Wprobe - Power/PAE calculation in Envelope Wireless analysis

    Category: Custom IC Design

    By UbltSR

    •

    started over 1 year ago

    0 replies • 600 views
  • Discussion

    Library Manager: Can it support e.g. bitmap pictures and libre office documents?

    Category: Custom IC Design

    By StephanWeber

    •

    updated over 1 year ago by henker

    1 replies • 2750 views
  • Discussion

    How to define Cell based on S-Parameters

    Category: Custom IC Design

    By spatz

    •

    updated over 1 year ago by Saloni Chhabra

    3 replies • 3427 views
  • Discussion

    View list and Stop list in Cadence PVS

    Category: Custom IC Design

    By thiruvenkata

    •

    updated over 1 year ago by ilyaF

    4 replies • 4668 views
  • Discussion

    Hierarchical LVS Issues or how to deal with LVS hierarchy

    Category: Custom IC Design

    By spatz

    •

    updated over 1 year ago by RobMan

    3 replies • 4793 views
  • Discussion

    Different PSS and Pnoise result with different Fund and sample_ratio settings

    Category: Custom IC Design

    By YutaoLiu

    •

    started over 1 year ago

    0 replies • 2911 views
  • Discussion

    The tran+stb simulation phase curve declines from -150 degree

    Category: Custom IC Design

    By liangqunshan

    •

    updated over 1 year ago by liangqunshan

    1 replies • 1070 views
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