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Custom IC Design

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  • Discussion

    In WSP, how to align different layout instances tracks in top level

    Category: Custom IC Design

    By Ganesh 213

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    updated over 9 years ago by Ganesh 213

    2 replies • 14861 views
  • Discussion

    QuickAlign "center" to "edge-center" deprecated in Layout 6.1.7?

    Category: Custom IC Design

    By dontpanic

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    updated over 9 years ago by Andrew Beckett

    8 replies • 9966 views
  • Discussion

    ADE-XL: How to (efficiently) sweep parameters over a "Statistical Corner"

    Category: Custom IC Design

    By dontpanic

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    updated over 9 years ago by dontpanic

    2 replies • 2312 views
  • Discussion

    IC6 constraining/placing matched transistors

    Category: Custom IC Design

    By stuso

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    updated over 9 years ago by Andrew Beckett

    12 replies • 6645 views
  • Discussion

    Inconsistency between time and freq. domain results in pss plot

    Category: Custom IC Design

    By VLSIiitm

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    •

    updated over 9 years ago by VLSIiitm

    1 replies • 14278 views
  • Discussion

    ADE-XL "Saving History" very slow

    Category: Custom IC Design

    By Rob Gregoire

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    updated over 9 years ago by Rob Gregoire

    10 replies • 4029 views
  • Discussion

    Using Edit-Component Display for annotating dc operating point

    Category: Custom IC Design

    By jdp721

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    updated over 9 years ago by Andrew Beckett

    1 replies • 14060 views
  • Discussion

    How to trigger call-back procedure when changing cell-name of existing instance?

    Category: Custom IC Design

    By Sheppy

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    updated over 9 years ago by Andrew Beckett

    4 replies • 16674 views
  • Discussion

    export def without component orientation

    Category: Custom IC Design

    By Polly

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    started over 9 years ago

    0 replies • 13024 views
  • Discussion

    how to varies the threshold voltage for mos transistor??

    Category: Custom IC Design

    By vishnu4830

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    •

    updated over 9 years ago by DeeMJ

    7 replies • 22249 views
  • Discussion

    Netlist schematic to Verilog: Preserve "var real" port type across entire netlist

    Category: Custom IC Design

    By jyang4

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    started over 9 years ago

    0 replies • 1237 views
  • Discussion

    Virtuoso Layout Editor net highlighting

    Category: Custom IC Design

    By apple419

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    •

    updated over 9 years ago by apple419

    2 replies • 15955 views
  • Discussion

    test vector creation for ATE

    Category: Custom IC Design

    By apple419

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    •

    updated over 9 years ago by apple419

    4 replies • 16785 views
  • Discussion

    Abstract Generator: Terminals not accessible, off-grid pins

    Category: Custom IC Design

    By marten

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    updated over 9 years ago by marten

    1 replies • 14635 views
  • Discussion

    middle-of-line (MOL) layers

    Category: Custom IC Design

    By vishnu4830

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 13512 views
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