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Digital Implementation

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  • Discussion

    clock gating

    Category: Digital Implementation

    By The Universe

    •

    started over 15 years ago

    0 replies • 14283 views
  • Discussion

    how to move FTerms

    Category: Digital Implementation

    By Nataraja G

    •

    updated over 15 years ago by BobD

    1 replies • 14696 views
  • Discussion

    How to identify clock network objects in the design?

    Category: Digital Implementation

    By Rajesh Vembu

    •

    updated over 15 years ago by BobD

    3 replies • 16695 views
  • Discussion

    set_dont_use/setDontUse

    Category: Digital Implementation

    By prathima

    •

    updated over 15 years ago by prathima

    2 replies • 5584 views
  • Discussion

    How to get Connectivity Information between given modules

    Category: Digital Implementation

    By Nataraja G

    •

    updated over 15 years ago by BobD

    8 replies • 20885 views
  • Discussion

    command for deleting Regions

    Category: Digital Implementation

    By surajece01

    •

    updated over 15 years ago by surajece01

    2 replies • 18320 views
  • Discussion

    question about Encounter Library Characterizer

    Category: Digital Implementation

    By Nathen

    •

    updated over 15 years ago by SindyZeng

    2 replies • 14771 views
  • Discussion

    How to make SoC Encounter export Verilog with VDD/VSS pins

    Category: Digital Implementation

    By LogicWizard

    •

    updated over 15 years ago by wally1

    3 replies • 2881 views
  • Discussion

    coupling capacitances not included in the spf file

    Category: Digital Implementation

    By asinghct

    •

    updated over 15 years ago by Quek

    1 replies • 16181 views
  • Discussion

    Missing net and Cell Names-exporting gds2 from encounter , importing it in Caliber

    Category: Digital Implementation

    By asinghct

    •

    updated over 15 years ago by asinghct

    16 replies • 22702 views
  • Discussion

    Validate CDB noise model file

    Category: Digital Implementation

    By deeps

    •

    updated over 15 years ago by deeps

    3 replies • 16499 views
  • Discussion

    How to find ThroughPin(s) for generated clock

    Category: Digital Implementation

    By MMode

    •

    updated over 15 years ago by MMode

    6 replies • 3715 views
  • Discussion

    Is sign off LVS check neccessary for Encounter based PnR

    Category: Digital Implementation

    By Greatrebel

    •

    updated over 15 years ago by Kari

    3 replies • 16026 views
  • Discussion

    die size reduction techniques

    Category: Digital Implementation

    By Rajesh Vembu

    •

    started over 15 years ago

    0 replies • 14278 views
  • Discussion

    Identifying Clocktree Cells

    Category: Digital Implementation

    By nv03

    •

    updated over 15 years ago by prathima

    1 replies • 14787 views
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