Logic Design

Latest Posts

Discussion

RTL_compiler SDF

Category: Logic Design

By archive
•
updated over 14 years ago by legolas

8 replies • 15884 views
Discussion

Black Boxes

Category: Logic Design

By AMit Raj
•
updated over 14 years ago by croy

1 replies • 13352 views
Discussion

Synthesizing 'x'

Category: Logic Design

By Tzachi Noy
•
started over 14 years ago

0 replies • 5421 views
Discussion

RTL Compiler: how to get all input ports except clock ports?

Category: Logic Design

By airland
•
updated over 14 years ago by grasshopper

1 replies • 18268 views
Discussion

RTL compiler: how to do bottom-up synthesis

Category: Logic Design

By airland
•
updated over 14 years ago by airland

4 replies • 15908 views
Discussion

Undesirable buffer insertion for constant pins attached to an instantiated hard macro

Category: Logic Design

By Brannon
•
updated over 14 years ago by grasshopper

4 replies • 14437 views
Discussion

error in waveform generation

Category: Logic Design

By lov sareen
•
updated over 14 years ago by croy

1 replies • 13360 views
Discussion

RC: clock gating

Category: Logic Design

By Yemelya
•
updated over 14 years ago by Yemelya

2 replies • 15686 views
Discussion

RTL Compiler: Does coding style influence synthesis result?

Category: Logic Design

By Tzachi Noy
•
updated over 14 years ago by grasshopper

1 replies • 14163 views
Discussion

not able to write logic

Category: Logic Design

By lov sareen
•
updated over 14 years ago by croy

1 replies • 12921 views
Discussion

what is the value for these parameters?

Category: Logic Design

By yongchen
•
started over 14 years ago

0 replies • 12704 views
Discussion

RTL Compiler: how to get units for load

Category: Logic Design

By yongchen
•
updated over 14 years ago by yongchen

4 replies • 15874 views
Discussion

RTL Compiler: How to locate registers with unconnected reset port

Category: Logic Design

By hnfq
•
updated over 14 years ago by hnfq

2 replies • 13778 views
Discussion

how to uniquify the designWare in LEC

Category: Logic Design

By richardsjsv
•
updated over 14 years ago by croy

2 replies • 14396 views
Discussion

RTL Compiler : Giving 1'b0 in synthesized netlist

Category: Logic Design

By deeps4
•
updated over 14 years ago by deeps4

5 replies • 3420 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.