Logic Design

Latest Posts

Discussion

RTL compiler inner clock definition

Category: Logic Design

By EvgeniySUAI
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updated over 14 years ago by EvgeniySUAI

6 replies • 9503 views
Discussion

cadence RTL compiler...WNS (Worse Negative slack)

Category: Logic Design

By ChInNi miSSing
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updated over 14 years ago by ChInNi miSSing

4 replies • 15827 views
Discussion

after synthesis, in gui_show plot some components are missing

Category: Logic Design

By ChInNi miSSing
•
updated over 14 years ago by grasshopper

1 replies • 13218 views
Discussion

rtl synthesis

Category: Logic Design

By vlsiproject
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updated over 14 years ago by grasshopper

2 replies • 13959 views
Discussion

Clock Gating: Pre or Post Control

Category: Logic Design

By moogyd
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updated over 14 years ago by moogyd

3 replies • 18313 views
Discussion

Design Compiler commands to RTL command Conversion

Category: Logic Design

By Electronic Guy
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updated over 14 years ago by Electronic Guy

2 replies • 14218 views
Discussion

Input port associated to Clock

Category: Logic Design

By sureshm
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updated over 14 years ago by grasshopper

1 replies • 15338 views
Discussion

RTL Compiler: "Clock Tree" Reports

Category: Logic Design

By moogyd
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updated over 14 years ago by sureshm

4 replies • 2191 views
Discussion

Long Run Times

Category: Logic Design

By sureshm
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updated over 14 years ago by grasshopper

6 replies • 14823 views
Discussion

RTL Compiler: Unavoid the tiecells from library

Category: Logic Design

By haikom
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updated over 14 years ago by grasshopper

1 replies • 13308 views
Discussion

Unconnected inputs after clock_gating insert_obs

Category: Logic Design

By maxb
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started over 14 years ago

0 replies • 12723 views
Discussion

RTL compiler version issue?

Category: Logic Design

By deeps4
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updated over 14 years ago by deeps4

2 replies • 13376 views
Discussion

naming on CSA module

Category: Logic Design

By tompy
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updated over 14 years ago by grasshopper

4 replies • 14476 views
Discussion

some components are missing in the gui plot after synthesis

Category: Logic Design

By ChInNi miSSing
•
started over 14 years ago

0 replies • 12595 views
Discussion

LEF in synthesis flow

Category: Logic Design

By diablo
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updated over 14 years ago by diablo

7 replies • 19193 views

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