Logic Design

Latest Posts

Discussion

RE: How to change the X and Y axis in OrCAD Probe?

Category: Logic Design

By Alok Tripathi
•
started over 14 years ago

0 replies • 14642 views
Discussion

TIP OF THE MONTH : Reporting similarity between two designs (new for v7.1!)

Category: Logic Design

By archive
•
updated over 14 years ago by MaheshSiddappa

1 replies • 15034 views
Discussion

RC -- how to report the hold viols ?

Category: Logic Design

By nozuey
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updated over 14 years ago by bmiller

4 replies • 5359 views
Discussion

starting RTL compiler and Encounter

Category: Logic Design

By jun1119
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updated over 14 years ago by grasshopper

1 replies • 16657 views
Discussion

RTL Compiler Error message [VLOGPT-46] [read_hdl]

Category: Logic Design

By naveenkumar
•
updated over 14 years ago by croy

1 replies • 17279 views
Discussion

problem with reading TCF - file in RC

Category: Logic Design

By Alex Kli
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updated over 14 years ago by grasshopper

3 replies • 4007 views
Discussion

"Word too long" error while running write_vectors step in Encounter test

Category: Logic Design

By krishcit
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updated over 14 years ago by Andy Hughes

3 replies • 2342 views
Discussion

LEC- CUT POINTS

Category: Logic Design

By battunvn
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updated over 15 years ago by croy

1 replies • 4840 views
Discussion

RC info message

Category: Logic Design

By PradyK
•
started over 15 years ago

0 replies • 14394 views
Discussion

RC area information

Category: Logic Design

By Alex Kli
•
started over 15 years ago

0 replies • 14395 views
Discussion

LEC - Not-mapped key points

Category: Logic Design

By AMit Raj
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updated over 15 years ago by croy

7 replies • 9252 views
Discussion

RTL Compiler Cell Recognition Problem

Category: Logic Design

By eklikeroomys
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updated over 15 years ago by eklikeroomys

4 replies • 16389 views
Discussion

Problems in custom design verification using LEC

Category: Logic Design

By sunkimi
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updated over 15 years ago by croy

3 replies • 16467 views
Discussion

RTL Compiler does not make use of "non-conventional" multiple-output cells

Category: Logic Design

By vdbem
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updated over 15 years ago by grasshopper

3 replies • 2385 views
Discussion

Instance limit for RTL compiler "L" version

Category: Logic Design

By Brandtechnik
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updated over 15 years ago by Brandtechnik

3 replies • 3910 views

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