Logic Design

Latest Posts

Discussion

RTL Compiler Error message [VLOGPT-46] [read_hdl]

Category: Logic Design

By naveenkumar
•
updated over 14 years ago by croy

1 replies • 17117 views
Discussion

problem with reading TCF - file in RC

Category: Logic Design

By Alex Kli
•
updated over 14 years ago by grasshopper

3 replies • 3709 views
Discussion

"Word too long" error while running write_vectors step in Encounter test

Category: Logic Design

By krishcit
•
updated over 14 years ago by Andy Hughes

3 replies • 2134 views
Discussion

LEC- CUT POINTS

Category: Logic Design

By battunvn
•
updated over 14 years ago by croy

1 replies • 4644 views
Discussion

RC info message

Category: Logic Design

By PradyK
•
started over 14 years ago

0 replies • 14297 views
Discussion

RC area information

Category: Logic Design

By Alex Kli
•
started over 14 years ago

0 replies • 14303 views
Discussion

LEC - Not-mapped key points

Category: Logic Design

By AMit Raj
•
updated over 14 years ago by croy

7 replies • 8623 views
Discussion

RTL Compiler Cell Recognition Problem

Category: Logic Design

By eklikeroomys
•
updated over 14 years ago by eklikeroomys

4 replies • 16077 views
Discussion

Problems in custom design verification using LEC

Category: Logic Design

By sunkimi
•
updated over 14 years ago by croy

3 replies • 16268 views
Discussion

RTL Compiler does not make use of "non-conventional" multiple-output cells

Category: Logic Design

By vdbem
•
updated over 14 years ago by grasshopper

3 replies • 2173 views
Discussion

Instance limit for RTL compiler "L" version

Category: Logic Design

By Brandtechnik
•
updated over 14 years ago by Brandtechnik

3 replies • 3674 views
Discussion

Unmapped point (not-mapped) in (R)

Category: Logic Design

By artoo
•
updated over 14 years ago by Aruna chowdary

2 replies • 17294 views
Discussion

Redirecting a command output to a file.

Category: Logic Design

By nozuey
•
updated over 14 years ago by bmiller

2 replies • 26508 views
Discussion

RTL Compiler: handling of system verilog interfaces

Category: Logic Design

By Pierre DN
•
started over 14 years ago

0 replies • 14684 views
Discussion

Bottom-up design.. Need to generate .lib or ILM for subblocks..

Category: Logic Design

By nozuey
•
updated over 14 years ago by smdunga

1 replies • 15138 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.