Logic Design

Latest Posts

Discussion

Unmapped point (not-mapped) in (R)

Category: Logic Design

By artoo
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updated over 15 years ago by Aruna chowdary

2 replies • 17610 views
Discussion

Redirecting a command output to a file.

Category: Logic Design

By nozuey
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updated over 15 years ago by bmiller

2 replies • 27121 views
Discussion

RTL Compiler: handling of system verilog interfaces

Category: Logic Design

By Pierre DN
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started over 15 years ago

0 replies • 14797 views
Discussion

Bottom-up design.. Need to generate .lib or ILM for subblocks..

Category: Logic Design

By nozuey
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updated over 15 years ago by smdunga

1 replies • 15283 views
Discussion

abort points in conformal

Category: Logic Design

By battunvn
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updated over 15 years ago by croy

1 replies • 16498 views
Discussion

Conformal LEC: performance during Hier_compare

Category: Logic Design

By AsicMax
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updated over 15 years ago by AsicMax

2 replies • 16143 views
Discussion

RTL_compiler SDF

Category: Logic Design

By archive
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updated over 15 years ago by legolas

8 replies • 19041 views
Discussion

Black Boxes

Category: Logic Design

By AMit Raj
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updated over 15 years ago by croy

1 replies • 15394 views
Discussion

Synthesizing 'x'

Category: Logic Design

By Tzachi Noy
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started over 15 years ago

0 replies • 5671 views
Discussion

RTL Compiler: how to get all input ports except clock ports?

Category: Logic Design

By airland
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updated over 15 years ago by grasshopper

1 replies • 21498 views
Discussion

RTL compiler: how to do bottom-up synthesis

Category: Logic Design

By airland
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updated over 15 years ago by airland

4 replies • 18614 views
Discussion

Undesirable buffer insertion for constant pins attached to an instantiated hard macro

Category: Logic Design

By Brannon
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updated over 15 years ago by grasshopper

4 replies • 17151 views
Discussion

error in waveform generation

Category: Logic Design

By lov sareen
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updated over 15 years ago by croy

1 replies • 15421 views
Discussion

RC: clock gating

Category: Logic Design

By Yemelya
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updated over 15 years ago by Yemelya

2 replies • 18707 views
Discussion

RTL Compiler: Does coding style influence synthesis result?

Category: Logic Design

By Tzachi Noy
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updated over 15 years ago by grasshopper

1 replies • 16623 views

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