• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
CDNS - double leaderboard script

Logic Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    CDL Import with extra parameters

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    2 replies • 16149 views
  • Discussion

    Clock gating

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 15681 views
  • Discussion

    How to trace flops with constant inputs in Conformal?

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 15260 views
  • Discussion

    Regarding sample dofile for in lec verify mode

    Category: Logic Design

    By admin

    •

    started over 18 years ago

    0 replies • 14333 views
  • Discussion

    RTL vs. gate netlist verification mapping problem

    Category: Logic Design

    By admin

    •

    started over 18 years ago

    0 replies • 14449 views
  • Discussion

    Gate-leve sim, sdf back annotation warnings

    Category: Logic Design

    By admin

    •

    started over 18 years ago

    0 replies • 16238 views
  • Discussion

    reporting gate count

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    2 replies • 19161 views
  • Discussion

    Can we read extracted timing model in RC

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 15100 views
  • Discussion

    RTL vs. gate netlist verification mapping problem

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 15717 views
  • Discussion

    Unmapped point (extra)

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 15796 views
  • Discussion

    inverted equivalent points

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 18726 views
  • Discussion

    help needed

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 14808 views
  • Discussion

    Non-equivalences due to different device.

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 14792 views
  • Discussion

    ncelab: *W,BIGWBS

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    4 replies • 4389 views
  • Discussion

    Gate-leve sim, sdf back annotation warnings

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    2 replies • 23005 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information