Logic Design

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Discussion

Genus : Tool coming out with "Killed"

Category: Logic Design

By sharadbrcm

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updated over 3 years ago by sharadbrcm

1 replies • 4852 views
Discussion

Best library structure (worklibs)

Category: Logic Design

By Ryic

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started over 3 years ago

0 replies • 10269 views
Discussion

xmvlog: *E,MULPAK

Category: Logic Design

By Yishay

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started over 3 years ago

0 replies • 5312 views
Discussion

Can Joules Report on wasted power on the inputs of a gated flop?

Category: Logic Design

By Falanke

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started over 3 years ago

0 replies • 10579 views
Discussion

Genus synthesis report

Category: Logic Design

By Kelly Yu

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updated over 3 years ago by Kelly Yu

2 replies • 14650 views
Discussion

Genus: Problem with long module name due to parameter types

Category: Logic Design

By pkarl

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updated over 3 years ago by pkarl

1 replies • 14725 views
Discussion

How to interpret area reported by Genus in mm2

Category: Logic Design

By abarajithan11

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started over 4 years ago

0 replies • 13209 views
Discussion

What kind of flops does state retention synthesis take?

Category: Logic Design

By iamKarthikBK

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started over 4 years ago

0 replies • 12117 views
Discussion

How to add logic when compile

Category: Logic Design

By BaoP

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started over 4 years ago

0 replies • 12308 views
Discussion

Check Constraints Problem

Category: Logic Design

By Dimitris Ant

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updated over 4 years ago by Dimo M

2 replies • 21645 views
Discussion

Tool for generating 'documentation friendly' schematics from RTL

Category: Logic Design

By gretzteam

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updated over 4 years ago by lstand

1 replies • 6897 views
Discussion

Default settings for cell mapping - Genus Synthesis (Legacy)

Category: Logic Design

By iamKarthikBK

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started over 4 years ago

0 replies • 6342 views
Discussion

Xcelium notation worklib:cell:view

Category: Logic Design

By Yakir

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started over 4 years ago

0 replies • 3907 views
Discussion

Get defines value from Xcelium simulation

Category: Logic Design

By Yakir

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started over 4 years ago

0 replies • 14379 views
Discussion

How to force RTL compiler to use a particular net name

Category: Logic Design

By deeps4

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updated over 4 years ago by Rameen

4 replies • 19219 views

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