Logic Design

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UNCONNECTED NETS in GENUS NETLIST!

Category: Logic Design

By AireenAmir

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updated over 4 years ago by Rameen

1 replies • 16143 views
Discussion

Genus VHDL 2008 Unconstrained array - Illegal element type for composite type. [VHDLPT-567] [read_hdl]

Category: Logic Design

By FlorianP

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updated over 4 years ago by FlorianP

2 replies • 10698 views
Discussion

RTL synthesis fault

Category: Logic Design

By nokta

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updated over 4 years ago by Rameen

6 replies • 21537 views
Discussion

What's the advantage for declaration different clock domain in Genus

Category: Logic Design

By NickK

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updated over 4 years ago by Dimo M

1 replies • 6685 views
Discussion

What is the command for opening the Xcelium Simulator ?

Category: Logic Design

By Sandeep29

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updated over 4 years ago by Dimo M

1 replies • 33775 views
Discussion

Compiling Xilinx libraries using Xcleium

Category: Logic Design

By rohanj

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updated over 4 years ago by rohanj

4 replies • 19053 views
Discussion

Reporting non-RC gated flops

Category: Logic Design

By Max Bjurling

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updated over 4 years ago by Max Bjurling

2 replies • 16306 views
Discussion

Genus - Hierarchy

Category: Logic Design

By Stratis

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updated over 4 years ago by Dimo M

1 replies • 8000 views
Discussion

VHDL IEEE Library not recognized by RTL Compiler or Genus

Category: Logic Design

By YuntaoLiu

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updated over 4 years ago by Dimo M

1 replies • 15597 views
Discussion

Conformal-ECO priority of picking freed cells and sparecells

Category: Logic Design

By Mihu

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started over 4 years ago

0 replies • 13819 views
Discussion

VHDL-613 error inside declarative region

Category: Logic Design

By carlosgewehr

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started over 4 years ago

0 replies • 13234 views
Discussion

Force cell equivalence between same-footprint and same-functionality hard-macros in Conformal LEC

Category: Logic Design

By Luca Pacher

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updated over 4 years ago by AndreasWiener

1 replies • 15643 views
Discussion

Genus advices on how to handle power and analog signals

Category: Logic Design

By abettati

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started over 4 years ago

0 replies • 14084 views
Discussion

Error in Cadence RTL Compiler when estimating Power using VCD

Category: Logic Design

By RileyDylan

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started over 4 years ago

0 replies • 13586 views
Discussion

how to debug the misbehaving scheduling of sequential logic

Category: Logic Design

By ChrisKAustin

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started over 4 years ago

0 replies • 13566 views

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