Logic Design

Latest Posts

Discussion

Check Constraints Problem

Category: Logic Design

By Dimitris Ant
•
updated over 5 years ago by Dimo M

2 replies • 25224 views
Discussion

Tool for generating 'documentation friendly' schematics from RTL

Category: Logic Design

By gretzteam
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updated over 5 years ago by lstand

1 replies • 8426 views
Discussion

Default settings for cell mapping - Genus Synthesis (Legacy)

Category: Logic Design

By iamKarthikBK
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started over 5 years ago

0 replies • 7783 views
Discussion

Xcelium notation worklib:cell:view

Category: Logic Design

By Yakir
•
started over 5 years ago

0 replies • 4271 views
Discussion

Get defines value from Xcelium simulation

Category: Logic Design

By Yakir
•
started over 5 years ago

0 replies • 16023 views
Discussion

How to force RTL compiler to use a particular net name

Category: Logic Design

By deeps4
•
updated over 5 years ago by Rameen

4 replies • 21499 views
Discussion

UNCONNECTED NETS in GENUS NETLIST!

Category: Logic Design

By AireenAmir
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updated over 5 years ago by Rameen

1 replies • 18727 views
Discussion

Genus VHDL 2008 Unconstrained array - Illegal element type for composite type. [VHDLPT-567] [read_hdl]

Category: Logic Design

By FlorianP
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updated over 5 years ago by FlorianP

2 replies • 12615 views
Discussion

RTL synthesis fault

Category: Logic Design

By nokta
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updated over 5 years ago by Rameen

6 replies • 25142 views
Discussion

What's the advantage for declaration different clock domain in Genus

Category: Logic Design

By NickK
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updated over 5 years ago by Dimo M

1 replies • 7795 views
Discussion

What is the command for opening the Xcelium Simulator ?

Category: Logic Design

By Sandeep29
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updated over 5 years ago by Dimo M

1 replies • 37661 views
Discussion

Compiling Xilinx libraries using Xcleium

Category: Logic Design

By rohanj
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updated over 5 years ago by rohanj

4 replies • 21775 views
Discussion

Reporting non-RC gated flops

Category: Logic Design

By Max Bjurling
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updated over 5 years ago by Max Bjurling

2 replies • 18608 views
Discussion

Genus - Hierarchy

Category: Logic Design

By Stratis
•
updated over 5 years ago by Dimo M

1 replies • 10024 views
Discussion

VHDL IEEE Library not recognized by RTL Compiler or Genus

Category: Logic Design

By YuntaoLiu
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updated over 5 years ago by Dimo M

1 replies • 17708 views

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