Logic Design

Latest Posts

Discussion

Handling abort points

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 15770 views
Discussion

TIP OF THE MONTH – Sept. 2007: Set-Up Automation

Category: Logic Design

By archive
•
started over 18 years ago

0 replies • 14176 views
Discussion

remove_assigns

Category: Logic Design

By archive
•
updated over 18 years ago by archive

2 replies • 17194 views
Discussion

RC see paths through the memories.

Category: Logic Design

By archive
•
updated over 18 years ago by archive

5 replies • 16356 views
Discussion

Issue with gated clock

Category: Logic Design

By archive
•
updated over 18 years ago by archive

3 replies • 16360 views
Discussion

Synthesis with ECSM or CCS

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 15939 views
Discussion

Complex cell

Category: Logic Design

By archive
•
started over 18 years ago

0 replies • 14237 views
Discussion

Forwarding RTL pragmas to Encounter

Category: Logic Design

By archive
•
updated over 18 years ago by archive

4 replies • 18579 views
Discussion

typedef enum in SV

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 15410 views
Discussion

how to initialize individual array elements ??

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 14869 views
Discussion

PLE adjusting in Rtl compiler

Category: Logic Design

By archive
•
updated over 18 years ago by archive

13 replies • 22501 views
Discussion

Multi corner workaround with RC?

Category: Logic Design

By archive
•
updated over 18 years ago by archive

5 replies • 18736 views
Discussion

generating SPICE netlist from verilog RTL using RC or nanoencounter

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 16683 views
Discussion

Can't simulate with gate delays.

Category: Logic Design

By archive
•
updated over 18 years ago by archive

2 replies • 1967 views
Discussion

No Hold Time Constrains Read In

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 14771 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.