• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
CDNS - double leaderboard script

Logic Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    setting rc constraints

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 14701 views
  • Discussion

    Error saying "Direction of module port... is not defined" bit blasted verilog netlist

    Category: Logic Design

    By archive

    •

    started over 18 years ago

    0 replies • 6801 views
  • Discussion

    Handling abort points

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 15866 views
  • Discussion

    TIP OF THE MONTH – Sept. 2007: Set-Up Automation

    Category: Logic Design

    By archive

    •

    started over 18 years ago

    0 replies • 14276 views
  • Discussion

    remove_assigns

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    2 replies • 17372 views
  • Discussion

    RC see paths through the memories.

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    5 replies • 16521 views
  • Discussion

    Issue with gated clock

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    3 replies • 16513 views
  • Discussion

    Synthesis with ECSM or CCS

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 16045 views
  • Discussion

    Complex cell

    Category: Logic Design

    By archive

    •

    started over 19 years ago

    0 replies • 14294 views
  • Discussion

    Forwarding RTL pragmas to Encounter

    Category: Logic Design

    By archive

    •

    updated over 19 years ago by archive

    4 replies • 18755 views
  • Discussion

    typedef enum in SV

    Category: Logic Design

    By archive

    •

    updated over 19 years ago by archive

    1 replies • 15496 views
  • Discussion

    how to initialize individual array elements ??

    Category: Logic Design

    By archive

    •

    updated over 19 years ago by archive

    1 replies • 14946 views
  • Discussion

    PLE adjusting in Rtl compiler

    Category: Logic Design

    By archive

    •

    updated over 19 years ago by archive

    13 replies • 22853 views
  • Discussion

    Multi corner workaround with RC?

    Category: Logic Design

    By archive

    •

    updated over 19 years ago by archive

    5 replies • 19046 views
  • Discussion

    generating SPICE netlist from verilog RTL using RC or nanoencounter

    Category: Logic Design

    By archive

    •

    updated over 19 years ago by archive

    1 replies • 16770 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information