Mixed-Signal Design

Latest Posts

Discussion

Resistance calculation of switch capacitor circuit

Category: Mixed-Signal Design

By mkza1002
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updated over 9 years ago by mkza1002

4 replies • 16719 views
Discussion

How can I give Addictive White Gaussian Noise(AWGN) as an INPUT?

Category: Mixed-Signal Design

By Surya Kiran
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updated over 9 years ago by Andrew Beckett

5 replies • 6306 views
Discussion

Using pPar("") in AMS simulation

Category: Mixed-Signal Design

By designguy
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updated over 9 years ago by Andrew Beckett

1 replies • 4140 views
Discussion

Verilog-AMS : Incorrect wreal net value of E2R connect module

Category: Mixed-Signal Design

By SimhanAnalog
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updated over 9 years ago by Andrew Beckett

1 replies • 15062 views
Discussion

Evaluating expression in monte carlo sim

Category: Mixed-Signal Design

By VIPPER
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updated over 9 years ago by Andrew Beckett

1 replies • 14312 views
Discussion

include function file in verilog-AMS

Category: Mixed-Signal Design

By Narasimhan90
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updated over 9 years ago by Andrew Beckett

1 replies • 16456 views
Discussion

VPI within analog section

Category: Mixed-Signal Design

By Fabian007
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updated over 9 years ago by Andrew Beckett

5 replies • 15859 views
Discussion

Difference marker in simvision

Category: Mixed-Signal Design

By SimhanAnalog
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updated over 9 years ago by SimhanAnalog

2 replies • 20136 views
Discussion

Advice on Efficient and Accurate E2R module

Category: Mixed-Signal Design

By acook
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started over 9 years ago

0 replies • 13823 views
Discussion

ADEXL measurement for temp drift of an output variable

Category: Mixed-Signal Design

By vamshiky
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updated over 9 years ago by Andrew Beckett

3 replies • 14108 views
Discussion

Noise analysis for FET transistors

Category: Mixed-Signal Design

By Patrick L
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updated over 9 years ago by Andrew Beckett

1 replies • 13277 views
Discussion

How to instantiate module ports by name when port bus defined individually - VerilogAMS

Category: Mixed-Signal Design

By SimhanAnalog
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updated over 9 years ago by Andrew Beckett

1 replies • 3012 views
Discussion

DCO test using Verilog A "unexpected statement "{""

Category: Mixed-Signal Design

By Yizhe Hu
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updated over 9 years ago by Andrew Beckett

5 replies • 2841 views
Discussion

ncsim with Ultrasim very slow for post layout simulation

Category: Mixed-Signal Design

By dogrush
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updated over 9 years ago by dogrush

2 replies • 13660 views
Discussion

VHDL-AMS VIEW LIST in ADE

Category: Mixed-Signal Design

By eppo
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updated over 9 years ago by Andrew Beckett

3 replies • 14835 views

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