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Latest Posts

  • Discussion

    *WARNING* Cut layer of viaDef 'M1_OD' should be of function 'cut', 'li' or 'passivationCut'.

    Category: Custom IC Design

    By shushan

    •

    updated over 15 years ago by Andrew Beckett

    7 replies • 8586 views
  • Discussion

    why is the constraint manager,which connected to HDL, being the state of ' read only'?

    Category: PCB Design

    By Churbill

    •

    updated over 15 years ago by Churbill

    2 replies • 4307 views
  • Discussion

    Allegro / Cadence PCB Editor symbol modifications

    Category: PCB Design

    By split63

    •

    updated over 15 years ago by redwire

    3 replies • 14521 views
  • Discussion

    environment variables

    Category: Custom IC SKILL

    By Michael Robinson

    •

    updated over 15 years ago by Michael Robinson

    2 replies • 16254 views
  • Discussion

    SPB16.3: Transferring Constraints from PCB to Router, has something changed?

    Category: PCB Design

    By mvonahnen

    •

    updated over 15 years ago by mvonahnen

    3 replies • 13491 views
  • Discussion

    high version to low version

    Category: PCB Design

    By kabalee

    •

    updated over 15 years ago by HSBM

    1 replies • 13909 views
  • Discussion

    UMC 0.18 µ m RF CMOS Process,models N_L18W500_18_RF/N_PO7W500_18_RF device widths

    Category: RF Design

    By rfpassion

    •

    started over 15 years ago

    0 replies • 1075 views
  • Discussion

    removing unused schematic folders from a design

    Category: PCB Design

    By circuitmonk

    •

    updated over 15 years ago by Aey2519

    2 replies • 14607 views
  • Discussion

    What format are these plots ?

    Category: PCB Design

    By Goblin59

    •

    updated over 15 years ago by Goblin59

    2 replies • 13323 views
  • Discussion

    VHDL Procedure Call from a Verilog Module

    Category: Functional Verification

    By ashfaqh

    •

    started over 15 years ago

    0 replies • 14078 views
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