• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      HASAN2024
      HASAN2024 55 Points
    • 2
      SD20251126912
      SD20251126912 50 Points
    • 2
      SM202511279440
      SM202511279440 50 Points
    • 4
      Don2009
      Don2009 45 Points
    • 5
      Aurel B
      Aurel B 41 Points
  • Leaderboard

    • 1
      steve
      steve 17,709 Points
    • 2
      oldmouldy
      oldmouldy 13,630 Points
    • 3
      eDave
      eDave 10,261 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    How to Toggle Metal Layer Visibility Sequentially with Bindkeys?

    Category: Custom IC Design

    By SS202502085313

    •

    updated 9 months ago by Andrew Beckett

    3 replies • 2990 views
  • Discussion

    How to get radiation patterns of Antenna array for a Time modulated Signal.

    Category: AWR Design Environment

    By SN202411058445

    •

    updated 9 months ago by SandyRF

    2 replies • 1479 views
  • Not Answered

    Nport_FV

    Category: AWR Design Environment

    By NF202501292154

    •

    updated 9 months ago by OscPn

    1 replies • 1139 views
  • Discussion

    Schematic creation popup skip

    Category: Custom IC SKILL

    By SimhanAnalog

    •

    updated 9 months ago by SimhanAnalog

    2 replies • 2431 views
  • Discussion

    Control position of instance placement in an ihdl imported schematic

    Category: Custom IC Design

    By mrharris

    •

    updated 9 months ago by Andrew Beckett

    1 replies • 2308 views
  • Answered

    DB Doctor

    Category: Allegro X PCB Editor

    By josephc

    •

    updated 9 months ago by JA202502071812

    8 replies • 7439 views
  • Answered

    Exporting and Simulating a Project From Analyst MWO to Analyst-MP gives Drastically Different Results

    Category: AWR Design Environment

    By Ken Seybold

    •

    updated 9 months ago by Ken Seybold

    1 replies • 1344 views
  • Answered

    Use wildcard entry for RefDes search

    Category: Allegro X Scripting - Skill

    By SambaKantipudi

    •

    updated 9 months ago by SambaKantipudi

    2 replies • 1017 views
  • Discussion

    vmsUpdateCellViews disable automatic symbol creation

    Category: Custom IC SKILL

    By SimhanAnalog

    •

    updated 9 months ago by SimhanAnalog

    2 replies • 2377 views
  • Discussion

    Finding EAD/ICT file for running parasitic Extraction in Virtuoso EXL

    Category: Custom IC Design

    By AL202502074331

    •

    updated 9 months ago by Andrew Beckett

    1 replies • 707 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information