• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      DavidJHutchins
      DavidJHutchins 190 Points
    • 2
      bdc66a938f164d
      bdc66a938f164d 88 Points
    • 3
      oldmouldy
      oldmouldy 80 Points
    • 4
      Aurel B
      Aurel B 77 Points
    • 5
      JCTEYSSIER0
      JCTEYSSIER0 75 Points
  • Leaderboard

    • 1
      steve
      steve 17,599 Points
    • 2
      oldmouldy
      oldmouldy 13,625 Points
    • 3
      eDave
      eDave 10,206 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    virtuoso VXL module generate problem

    Category: Custom IC Design

    By Skill Designer

    •

    updated over 12 years ago by skillUser

    2 replies • 13685 views
  • Discussion

    problems with report_timing when using user defined path groups

    Category: Digital Implementation

    By malicad

    •

    started over 12 years ago

    0 replies • 12926 views
  • Discussion

    Die height in stacked die

    Category: Allegro X APD

    By design58

    •

    updated over 12 years ago by Tyler

    1 replies • 14616 views
  • Discussion

    single analysisType does not work with SIAware flag in ETS

    Category: Digital Implementation

    By malicad

    •

    started over 12 years ago

    0 replies • 13162 views
  • Discussion

    Save all pads from open symbol into new folder

    Category: PCB Design

    By TAyres

    •

    updated over 12 years ago by TAyres

    2 replies • 12878 views
  • Discussion

    pnoise simulation setup questions (again?)

    Category: RF Design

    By eeask

    •

    updated over 12 years ago by eeask

    8 replies • 16780 views
  • Discussion

    PSpice A/D accuracy in V16.3?

    Category: PCB Design

    By makeit

    •

    updated over 12 years ago by makeit

    2 replies • 1092 views
  • Discussion

    Pls give me a suggestion to solve the "error(spmhod-29)"

    Category: PCB Design

    By ping2murali

    •

    updated over 12 years ago by ping2murali

    2 replies • 5668 views
  • Discussion

    need help in formal verification with IEV tool

    Category: Functional Verification

    By BharathECE

    •

    updated over 12 years ago by StephenH

    1 replies • 13472 views
  • Discussion

    Problem while extracting total noise of a MOS (Flicker+thermal)

    Category: Custom IC Design

    By RAO VINAY

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 972 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information