• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      OleKri
      OleKri 50 Points
    • 1
      HP20260601263
      HP20260601263 50 Points
    • 3
      avant
      avant 45 Points
    • 4
      steve
      steve 35 Points
    • 5
      RM202605273230
      RM202605273230 25 Points
  • Leaderboard

    • 1
      steve
      steve 17,859 Points
    • 2
      oldmouldy
      oldmouldy 13,830 Points
    • 3
      eDave
      eDave 10,381 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Not Answered

    Orcad Capture TCL scripting documentation

    Category: Allegro X Scripting - TCL

    By Diego cmre

    •

    updated 4 months ago by CadAP

    3 replies • 8025 views
  • Suggested Answer

    ORCAP-1616 INVALID REFERENCE

    Category: Allegro X Capture CIS

    By TM202601138148

    •

    updated 4 months ago by TechnoBobby

    1 replies • 779 views
  • Answered

    Productivity Toolbox - Post Processing - ODB++ Generation

    Category: Allegro X PCB Editor

    By ersgfserg645

    •

    updated 4 months ago by ersgfserg645

    2 replies • 1121 views
  • Answered

    SysCap - "Swap" Net Name"

    Category: Allegro X Scripting - TCL

    By JohnFr38

    •

    updated 4 months ago by MZ20250602835

    19 replies • 14545 views
  • Discussion

    How to set all layers of a specific layer name visible, regardless of layer purpose

    Category: Custom IC SKILL

    By cvictoria

    •

    updated 4 months ago by cvictoria

    2 replies • 1914 views
  • Discussion

    FATAL: The following branches form a loop of rigid branches (short) when added to the circuit

    Category: Custom IC Design

    By TS20260112292

    •

    started 4 months ago

    0 replies • 1215 views
  • Suggested Answer

    CADSTAR TO ALLEGRO CONVERSION

    Category: Allegro X PCB Editor

    By RR202509215846

    •

    updated 4 months ago by JuanCR

    1 replies • 1304 views
  • Answered

    Orcad capture did not open

    Category: Allegro X Capture CIS

    By KM202601127752

    •

    updated 4 months ago by oldmouldy

    7 replies • 2693 views
  • Discussion

    How display SOA report of simulation in ADE

    Category: Custom IC Design

    By Phd SA88

    •

    started 4 months ago

    0 replies • 1219 views
  • Discussion

    How to short all the internal nets to VSS with skill

    Category: Custom IC SKILL

    By Mooh

    •

    updated 4 months ago by Mooh

    2 replies • 1781 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information