• Discussion

  How to put via in the center of BGA pins Locked

  16077 views
  5 replies
  Latest over 7 years ago
  by riklee
• Discussion

  Assura LVS: different nets in pad's schematic (vdd3r) and it's layout (vdd3r1 and vdd3r2) and using joinableNet function. Locked

  638 views
  0 replies
  Started over 7 years ago
  by Fami
• Discussion

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  14402 views
  1 reply
  Latest over 7 years ago
  by steve
• Discussion

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  3 replies
  Latest over 7 years ago
  by BK2018
• Discussion

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  15447 views
  2 replies
  Latest over 8 years ago
  by noob1
• Discussion

  saveNetlist option changing view to functional from schematic- Innovus to Calibre Locked

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  3 replies
  Latest over 8 years ago
  by Andrew Beckett
• Discussion

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  15542 views
  2 replies
  Latest over 8 years ago
  by DanielDing
• Discussion

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  2 replies
  Latest over 8 years ago
  by tmd63
• Discussion

  how to identify spectre simulator version from SKILL? Locked

  15906 views
  1 reply
  Latest over 8 years ago
  by Andrew Beckett
• Discussion

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  14534 views
  1 reply
  Latest over 8 years ago
  by Andrew Beckett
• Discussion

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  17015 views
  7 replies
  Latest over 8 years ago
  by oldmouldy
• Discussion

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  3 replies
  Latest over 8 years ago
  by aarthymani
• Discussion

  Coloring SKILL AppForm fields Locked

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  2 replies
  Latest over 8 years ago
  by sbilalov
• Discussion

  eye diagram problem Locked

  17065 views
  2 replies
  Latest over 8 years ago
  by ManuelSuarez
• Discussion

  Verilog-A import variables from file Locked

  19153 views
  5 replies
  Latest over 8 years ago
  by Andrew Beckett