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With DAC and other events during May and June, I am only now wrapping up stuff I wanted to write about from EDPS in Monterey. Cadence's T.C.Lin presented about the importance of system-level power and ended up with a recipe of how to do it.

I won...

The Allegro 17.2-2016 release, the largest in the past 10 years, became available in late April 2016. Since 17.2-2016 includes a database change that usually happens with a dot zero release, many of you may be wondering when the right time to migrate to this new release is.

Included below is an overview of the Top 10 reasons to move up to the Allegro 17.2-2016 release, so that you can better understand the value of each…

Modern fabs use 300mm (12") wafers. Older fabs have used 200mm (8") wafers since the early '90s, starting with IBM Fishkill's pilot with Siemens to build 64Mb DRAM in 1990. Before that, we had 5" wafers (150mm), and if you go back far enough in history...

Growing deployment level of 10 Gigabit Ethernet in datacenters and automotive infotainment is driving the demand and the connectivity needs of a broad range of high-end, energy-efficient networking and computing applications.

Energy-efficient networking in server area basically means elimination of packet loss, server virtualization with support for several applications and operating systems on a server; all by defining…

My docking station with the rat’s nest of wires dangling from behind it could be going the way of the Dodo bird soon, thanks to USB Power Delivery (PD) protocols and USB Type-C connectors.

The traditional docking station that we all know and hate, typically looks something like the picture below.

This is a photo of my docking station at work. These docking stations have 3 main problems:

1. There is a mess of…

With the 16.6-2015 Allegro PCB Editor release, the Snake pattern router can be enabled from the context menu of the Add Connect command. This functionality provides the ability to route through hex pattern packages utilizing arc routing, which has been greatly improved compared to the existing prototype pattern generator. Simply enable Snake mode via the RMB and Add Connect will detect a hex pattern pin/via field and…

The Monday before SEMICON West starts, there are two events that run in parallel in the Marriott Hotel. One is imec's US technology forum. Since I already attended the two-day version in Brussels, and wrote about it over the last couple of months, I attended...

Cadence was awarded with the IEEE Donald O. Pederson Best Paper Award—EDA’s most prestigious recognition of its kind—for the best paper published in IEEE Transactions on CAD over the past two years. 

The paper, “Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space”, was part of a collaboration with Carnegie Mellon University.…

In this week's Whiteboard Wednesdays video, Samer Hijazi discusses bringing deep learning to embedded devices.

https://youtu.be/1bi9Cg0tp6o

This year's Linley Mobile and Wearables Conference is coming up next week on July 26 and 27 in the Hyatt in Santa Clara. I'm sure Linley Gwenap is furiously rewriting his keynote on the mobile industry in the light of Softbank's acquisition of ARM, announced...

PCI-SIG Developers Conference 2016 is now history, taking place at the Santa Clara Convention Center at 28^th-29^th June, once again proving it’s not an event you want to miss. With PCIe 4.0 standard maturing, we’re seeing a lot of action in the market, though there are questions that have to be answered. 

There were questions about PCIe 5.0, and though it will become an important project, the SIG wisely is…

Over the weekend it seems that Softbank has closed a deal to acquire ARM Holdings (what we in the industry simply think of as ARM) for an all-cash deal for around $32B. The deal is expected to be formally announced on Monday, but since the Wall Street...

Chris Rowen, the CTO of the Cadence IP group, wrapped up the recent seminar in Las Vegas (see Breakfast Bytes for the last three days) by giving a vision for the future of neural networks and deep learning.

The technology is advancing fast but there...

The winners of the Tensilica Xtensa Embedded DSP Design Contest have been announced! The winning team members from CMR Institute of Technology, Bengaluru and Bangladesh University of Engineering and Technology, Dhaka received a HTC Desire 620G mobile...

The German Traffic Sign Benchmark actually has the signs divided into groups: speed limits, danger signs, and so on. It turns out that humans make far fewer errors between groups than within groups. They might mistake a 30kph speed limit sign for an 80kph...

Functional Coverage is one of the main means to measure the quality and progress of the verification project. We define coverage models, run semi-random tests, and every once in a while analyze the coverage report to decide “are we there yet?”.

When talking about “coverage closure”, people tend to talk about generation, how we create the data that will fill the coverage. In this blog, we discuss the definition…

Poland is a country with long tradition in microelectronics education and research. During the time of Iron Curtain when the universities were controlled by the government, the AGH University in Cracow was responsible for building microelectronic circuits...

Cadence Academic Network is supporting for years PRIME (PhD Research in Microelectronics and Electronics) and SMACD (Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design) conferences, so we were quite happy that both...

Convolutional neural nets (CNNs) are not programmed in the traditional sense, but rather they are trained. The challenge to doing this is that you need a lot of good data which is already classified as the training material.

The process is not that different...

My team recently had the privilege of hosting first year undergraduate students aka soon-to-be brilliant engineers from Pohang University of Science and Technology (POSTECH), Korea. On June 27 at 10 AM, a group of 35 engineering students and two professors...

Hope you read my previous blog on Cadence Academic Network sponsoring all the student activities and sponsorships at DAC this year. More than 100 students from around the world received the travel grants (sponsorships) and travelled to DAC Austin this...

In this week's Whiteboard Wednesdays video, Chung Huang summarizes his presentation from CDNLive Silicon Valley on gauging quality of signals using the eye diagram. To view his CDNLive presentation, please go to: https://www.cadence.com/cdnlive/na/2016/Pages/proceedingssummary.aspx. Refer to session DES204: Complexities in Developing a High-Performance DDR Subsystem at 3200Mbps on 16FF+.

https://youtu.be/kfCReND…

Neural networks are hot. Las Vegas is hot, too. And there is a connection. In late June, one of the major conferences for the field, Computer Vision and Pattern Recognition (CVPR), is held there. On the Sunday before, Cadence ran a half-day training course...

This doesn’t have much to do with Cadence or semiconductors. It has a lot to do with Japan, but Japan isn’t the force it used to be in semiconductors. They have gradually rolled a lot of their semiconductor companies up into Renasas, and their DRAM operations...

Cadence and ARM have created an IoT IP reference sub-system that can speed system development, enabling rapid prototyping and reducing time to market. The sub-system contains a processor and a set of peripherals that are typical for IoT sensors, giving a design team access to required functionality. Thus, the engineering effort is spent configuring the system, connecting the data stream to the cloud, and developing the…