Community

The 16.6 Allegro PCB Editor ‘DRC by Window’ command is an alternative to running DRC update at the full design level. As the name suggests, the command is limited to checking the elements within the extents of a user-defined selection window. On large, highly constrained designs where database performance is problematic, one can simply disable ‘On-line’ DRC mode if favor of this ‘On-demand’ method. …

In this week's Whiteboard Wednesdays video, the second in a three-part series, Pulin Desai goes into more detail on the function of each individual block within a camera subsystem.

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty discusses why LPDDR4 is the right choice for automotive memory designs.

By default, the 16.6 Allegro PCB Editor ‘Add Connect’ command generates routes when a pick is made on database elements like pins or vias, but also when a pick is made in open or black space. Designers who push the mouse fast and hard frequently make false picks and are forced to opt out of the command then refine the pick to a logical element like a pin or rat line. Some designers may embrace the open space pick concept…

One of the famous quotes of Brian Kernighan is: "Debugging is twice as hard as writing the code in the first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not smart enough to debug it". Well, I am not really sure he meant that no one is smart enough to debug one’s own code; however, he did mean that debugging is hard, if not even harder than coding. Hence, you want to get any…

In this week’s Whiteboard Wednesdays video, Chris Rowen explains the benefits of extending a processor’s instruction set to achieve higher performance and lower energy.

https://youtu.be/bzoXDAKinRI

There’s no denying that USB Type-C is the fastest adopted specification in the history of USB. Just by looking at the number of companies implementing the specification that was released only 10 months ago, one can see that this is truly the next big thing.

Despite such a short period after specification approval, there are already some devices and adapters available in the market, and the following months, or…

In this week's Whiteboard Wednesdays video, Pulin Desai provides an overview of a camera subsystem used in mobile, automotive, security, and PC applications.

https://youtu.be/vtC9Sq1xVp8

We're happy to have guest blogger Thorsten Dworzak describe how he added anonymous methods to the vlab_util package from Verilab. So here it goes:

Many programming languages like Python, Perl, and Ruby support anonymous methods[1], typically through classes or other constructs representing a block of code. These are useful to construct code by a higher-order method or to be used as arguments by higher-order methods…

Max cavity size and max cavity component count were offered as reports in the 16.5 release and are now available as DRCs in the 16.6 release of Allegro PCB Editor. Fab houses supporting embedded component manufacturing offer design guidelines on cavity usage. 

Consider a PCB with the following characteristics. Layer SIGNAL_7 is displayed where you see two merged cavities on the left as the result of Cap placement combined…

In this week's Whiteboard Wednesdays video, Lou Ternullo takes a closer look at what to consider when you are considering specialty memories, such as Wide I/O, HBM, and HMC.

https://youtu.be/vJi13D8mNSI

You still have a chance to get a paper accepted at the premier conference for memory technology—MemCon 2015.

Yes, on Tuesday, October 13, 2015, the brightest minds in memory technology will meet again at the Santa Clara Convention Center. The call for papers closes Friday, so it’s time to think about how you can further your career and showcase your understanding of key memory technologies.

See the full…

When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But sometimes there is a need to know the exact multi-value logic, or to write an mvl value (e.g., init the signal to Z).
For this purpose, the e language defines the mvl type – a predefined enumerated type, with values of MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, and MVL_N (based on the VHDL std_logic type).

If you need…

The art of expressing hardware functionality through constraint language is often one of the trickiest parts of functional verification. Unlike procedural actions that are executed locally one by one, constraints are scattered declarative entities that define the rules for the gen actions. Therefore you don't necessarily see clearly how constraints are impacting the generation. This situation opens the door for occasional…

Hi Everyone,

Last time we got a quick look at The Innovus Standard Flow. Now I'd like to show you a bit more detail about some of the major steps. One of the new concepts in Innovus is how placement and pre-CTS timing optimization are now combined and interleaved. The GigaPlace placement engine is also new, and you will learn about its features. Click below to play the video (you'll need an active support.cadence.com…

In this week's Whiteboard Wednesdays video, Gopi Krishna defines and describes how Address Translation Services is implemented in a system.

https://youtu.be/yOSALM5X1ZM

The PCI-SIG Developers Conference happening today and tomorrow will be yet another exciting PCI-SIG event that Cadence is proud to participate in. We’ve been attending and showcasing technology at these conferences for many years now, sharing news and insights about our verification IP, controllers, and PHY solutions.

Cadence was the first commercial PCI Express 3.0 IP provider, and has continued that tradition…

There is a team at Cadence working on developing the next generation of Cadence documentation and Help interface.  After rolling your eyes at this statement, I'd really like you to take 10 minutes to complete our brief (honest) survey to help us improve our documentation delivery in the future. 

Here's the link: Cadence Documentation Survey

And in case you haven't looked under the Help menu in your Virtuoso window…