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Partial Design Simulation aims at unifying the PCB and simulation flow by enabling the designer to use a single schematic for both simulation and PCB implementation. This gives the designer the ability to work with a larger design that may contain portions that will never be simulated in Allegro AMS Simulator, and also allows different circuits (in the design) to be simulated with different simulation profiles.

Using…

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly for mobile computing applications.  Customers tell us that's because it provides multiprocessor support and hardware based coherency while consuming only a small amount of power.  In our experience the majority of A15 designs are also adopting the new ACE protocol due to their need for a fast and reliable coherency scheme. 

To…

In a prior Team Verify post, Application Engineer Bin Ju talked about several applications of "Assertion Driven Simulation (ADS) in the Wild".  In the following tech tip, allow me (Chris Komar, right) to focus on a common thread through each of her stories: the need to quickly bring-up a design without having to write any throw-away RTL code.  One neat trick that supports this is a handy capability in Incisive…

A NetGroup is a collection of nets. The nets in a NetGroup can be scalar, vector or a combination of both. You can create a NetGroup that consists only of nets (like a bus). You can also create a NetGroup that consists of nets (scalar and/or vector), consists of buses, and consists of other NetGroups. By definition, a NetGroup is a completely heterogeneous collection of nets. The Net group option in the 16.5 release of…

Some of the enhancements to the Allegro Design Workbench (ADW) 16.5 release were introduced in the 16.3.1 release. The 16.5 version has expanded on these with an emphasis on increased performance.

The main new enhancements are:

• A new robust server is used
• Much improved server performance
• Lower management overhead
• Server Monitoring
• Mail Notifications
• XML based

Read on for more details…

The following provides a high-level…

In the previous posting Introduction to Classes -- Part 1 we introduced the problem of solving the Sudoku puzzle. I want to show a solution to this puzzle in SKILL++. Doing so, I'll break the problem up roughly into four parts.

• Represent the structure of the data
• Initializing
• Displaying the state
• Searching for a solution

Here is a top-down view of the solution algorithm.

(defun…

The 16.5 release of the Allegro System Connectivity Manager (SCM), also known as Allegro System Architect (ASA), has been enhanced to view implicit power pins in the Component Connectivity Pane (CCP).

This is required for control over the power pins for the design with dies or FPGAs where an ECO is required. This is also required in the co-design flow for SiP where connectivity changes are updated using the ECO Netlist…

Accurate static analysis and complete coverage of the functional space remain very challenging for mixed-signal designs.  The functional verification of mixed -signal designs has never been completely possible.

It is very common to use behavioral models of analog/mixed-signal blocks during the full chip functional verification stage, and to use .lib timing models during the physical implementation stage. There…

All Allegro PCB Editor designers know about the uprev process to migrate PCB .brd files from prior SPB releases to a newer release. The Allegro Design Entry HDL (DEHDL) designers rarely need to uprev. With the 16.5 release, however, you will need to uprev designs.

The 16.5 release includes major architectural changes aimed at providing a Design Aware DEHDL with a dynamic connectivity model. In the new architecture, there…

In Silicon Valley there is a popular fitness program called "Boot Camp" where people volunteer to be run through rigorous exercises by a demanding instructor, analogous to what armies around the world do bring new recruits up to the desired physical fitness standards.  Team Verify has a similar "boot camp" program where we rapidly train engineers in Formal and assertion-based verification (ABV) techniques.…

The N-queens issue is a challenging but standard puzzle when it comes to the world of constraint solving. It's a generalization of the 8-queens puzzle, whose description can be found in detail in Wikipedia (http://en.wikipedia.org/wiki/Eight_queens_puzzle.)  The challenge is to place N queens on an NxN chessboard in such a way that no pair of queens can attack each other.  For those unfamiliar with chess rules, this…

Open solutions are just curiosities until the ecosystem figures out how to turn them into money.  Java and Linux are good examples of that.  When they first hit the "open" space, they were interesting technical solutions to interoperability (Java) and breaking the proprietary operating system monopoly (Linux).  It's only when companies started wrapping products and services around them that they really…

Inspired by Brian Fuller's cross-country "Drive for Innovation", last week I jumped at an opportunity to head out and visit customers in the heartland of America.

Here were the common themes heard during the trip:

(1) Discovering Power People Didn't Know They Already Have
A lot of people don't realize that support for the things they need to do are actually in our products already (in some cases, it's been…

ACE is here. Are you ready?

Designers of multimedia smartphones, tablets, and other mobile computing devices face greater challenges than ever. They have to deliver ever more capable and responsive systems, yet must also consume the least amount of power possible -- certainly no more than their competitors.To achieve these goals, designers have been employing multi-processor architectures for many years. However, the need…

In the previous couple of SKILL for the Skilled postings, we looked at some of the features of SKILL++. In fact, we saw local functions, higher-order functions, and lexical scoping. Still another set of features of SKILL++ is called the SKILL++ Object System. This system provides a standardized way of implementing object oriented SKILL applications.

Object Orientation

An Object System is a programming language…

The following question has come up in comments: "How do I measure F_max for an MOS transistor?" The measurement methodology -- testbench, analysis, calculator setup, stimulus, etc.-- does not change whether you are measuring bipolar transistors...

How many times have you wanted to look at a certain standard cell in the Encounter Digital Implementation (EDI) system, so you go hunting around the design to find one, or use the Design Browser to find one? Then you turn off the nets and special nets to see only the contents of the cell. Or, maybe the cell type you wanted to look at is not even in your netlist currently. Maybe you want to look at an INVX4, but there…