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Verification: Virtual Flash Memory Gets Real

Steve Brown

This week's Flash Memory summit will not only highlight the IP Cadence delivers, but will touch on innovative application of virtual prototype technology for Flash Memory firmware and system development. Developing complex memory controllers...
- 8 Aug 2011
System, PCB, & Package Design : What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!

Jerry GenPart

Currently, many of the SPB products support extended nets, better known as Xnets. Xnets are created automatically when a signal model is assigned to a component and that signal model defines that a connection is to be made between two pins of the component. This creates an Xnet that connects the nets that are assigned to these two pins.
When an Xnet is created, all of the electrical constraints on the nets that form the…
- 8 Aug 2011
RF Engineering: Guidelines for Setting Pnoise/HBnoise Sidebands to Get Accurate Results

Tawna

I get quite a few questions from designers along the lines of "How do I set the number of pss/hb harmonics and pnoise/hbnoise sidebands in order to get accurate results?" Here are some general guidelines that I follow:
The number of sideban...
- 5 Aug 2011
Verification: A Must Read: the ARM Cortex-A Programmer's Guide

jasona

For the last couple of years, I have been getting a lot of e-mail from different LinkedIn groups. I'm interested in groups like Android, Embedded Linux, ARM, EDA Bloggers, and more. A majority of the days I don't have time to read much (or...
- 4 Aug 2011
SoC and IP: Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features

archive

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post.
What is SR-IOV? Briefly, SR-IOV is a specification that allows a PCIe device to appear to be multiple separate physical PCIe devices. PCI-SIG created and maintains the SR-IOV specification…
- 3 Aug 2011
System, PCB, & Package Design : What's Good About PCB SI Design Setup and Audit? 16.5 Has MANY New Enhancements!

Jerry GenPart

Many of the problems that customers encounter today when running a signal integrity (SI) analysis tool are caused by the design not being properly set up. The Allegro PCB SI tools require information that is specific to the tool, and it must be available before the tool will function correctly.
Today there is a Setup Advisor command whose purpose is to help you set up the design correctly. Although this command is useful…
- 2 Aug 2011
Verification: The Return of the Son of Real-World Assertions

tomacadence

I've received some nice feedback on my previous two posts about real-world situations that would benefit from assertions, so I will forge ahead with a few more examples. Last time I mentioned the DMV clerk who told me that glasses were required while driving if one eye was below the threshold but not if one eye was completely devoid of vision. One reason I remember that incident so clearly is that the clerk apparently…
- 1 Aug 2011
Analog/Custom Design: Virtuoso Analog Design Environment XL – Data Everywhere, But You Have a Review in 10 minutes, Now What?

archive

In my previous blogs, I talked about productivity enhancing features of Virtuoso Analog Design Environment XL and how designers can take advantage of these capabilities to design complex custom analog ICs. The Virtuoso Analog Design Environment XL multi-test bench environment, specification compliance and statistical analysis tools allow designers to cover the design space in a fast and efficient manner. Compiling and…
- 29 Jul 2011
SoC and IP: Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)

archive
This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.

Highlights:
The Cadence PCI Express 3.0…
- 28 Jul 2011
Verification: Four Uses for the Venerable Virtual Platform UART

jasona

The Universal Asynchronous Receiver/Transmitter (UART) is one of the oldest hardware peripherals, and yet it is is still present in many embedded systems created today. I'm not sure when it was invented, but Wikipedia says it was designed by Go...
- 27 Jul 2011
System, PCB, & Package Design : What's Good About APD’s Assembly DRCs? You’ll Need the 16.5 Release to See!

Jerry GenPart

Prior to the Allegro Package Designer (APD) 16.3 release, Design Rule Check (DRC) markers created by Assembly Rule Checks had to be external DRC markers since no constraint IDs were associated with the ADRC constraints. In the 16.3 release, Constraint IDs were created for each of the rules. It enabled us to make a change to DRC markers. For the 16.5 release, each Assembly DRC (ADRC) rule gets its own marker based on constraint…
- 26 Jul 2011
Verification: ARM Generic Interrupt Controller HOWTO

jasona

Way back in 2004, I wrote a book called Co-Verification of Hardware and Software for ARM SoC Design. At that time the world revolved around AHB and the ARM926EJ-S was a popular CPU. All ARM CPUs used two interrupt signals, nIRQ and nFIQ. The nIRQ ...
- 22 Jul 2011
Verification: Some Reflections on the Development of UVM World

tomacadence

In a recent blog post, I celebrated our donation of the Cadence-developed UVM World community Web site (www.uvmworld.org) to Accellera, the standards organization that owns and evolves the Universal Verification Methodology (UVM). It makes sense for us to work with other Accellera members to make this site even better and even more comprehensive going forward. As I celebrated the success of UVM World, I found myself…
- 22 Jul 2011
Verification: Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media

jvh3

At DAC I had the honor of being interviewed by EE Times editor Brian Fuller on my experiments with social media to connect to the communities of engineers that use the products and capabilities I help bring to market. Specifically, I shared with Brian the channels I've seen work well so far, which ones are starting slow but are still promising, and ones which are just not a fit. We also discuss what the future may…
- 21 Jul 2011
Verification: Enterprise Planner - CSV Import Tech Tip

Team MDV

Are you interested in an automating your directed or random test list that you manually maintain in MS Excel? Or are you looking to connect your coverage results automatically back onto those tests? Enterprise Planner, the verification plan creator utility within Incisive Enterprise Manager, can save you 50% of the management overhead associated with keeping track of your tests, and automatically back annotate coverage…
- 15 Jul 2011
Verification: Creating SystemC TLM-2.0 Peripheral Models

TeamESL

Over two years ago, I made some experiments and raised some requirements for an effective Virtual Platform IP authoring tool. Even with the passage of time, some people seem to find it useful as I regularly get questions about it. It is more than tim...
- 14 Jul 2011
Digital Design: Five-Minute Tutorial: Finding EDI Videos

Kari

I've seen a few requests in the forums asking about EDI videos. Today I will show you how to find them on the Cadence Support website.

First, go to support.cadence.com. One of the menus across the top is called "Resources". Hover your mouse over this menu and click "Video Library" near the bottom:

On the next page that comes up, click "View all content for all products" in the lower-right:…
- 14 Jul 2011
System, PCB, & Package Design : What's Good About Allegro GRE Route Around Etch Shapes? See For Yourself in 16.5!

Jerry GenPart

This new 16.5 Global Route Environment (GRE) functionality was designed to allow the router to obey plane shapes that are found on signal layers. This is especially useful when a user is trying to work a breakout/route solution and maintain the power integrity of today's high power chips.

This functionality has some ramifications -
1. It is global in nature. In other words, it cannot be controlled at the bundle level…
- 13 Jul 2011
Verification: More Examples of Missing Real-World Assertions

tomacadence

Back in May, I published a blog post with examples of real-world situations that seemed to be begging for assertions to improve them. I mentioned misdirected advertising, mis-scheduled TV programming, and nonsensical cooking directions. So far I've had some positive feedback and no one calling me an idiot for straying from strictly technical topics. Therefore, I'd like to bring in a few more examples that have…
- 12 Jul 2011
Analog/Custom Design: Things You Didn't Know About Virtuoso: Viva ViVA!

stacyw

I realize that I have been quite remiss in that I have not yet blogged about the new all-singing all-dancing ViVA waveform viewer which was released in IC6.1.5 back in January. All right, it doesn't really sing and dance -- but would you really want it to? Really? Submit an enhancement request and we'll see what we can do...
In the meantime, I can tell you that ViVA (oh, that's Virtuoso Visualization and A…
- 8 Jul 2011
Verification: Celebrating the Success of the UVM World Web Site

tomacadence

In case you missed it, Cadence issued a press release last week announcing that we have donated the UVM World Web site (www.uvmworld.org) to Accellera. This is a significant event for at least three reasons. First, in light of Accellera's recent release of the Universal Verification Methodology (UVM) standard, it is the right time for the organization the take control of the primary Web source for UVM information. It…
- 6 Jul 2011
Analog/Custom Design: Synchronizing Designs and Behavioral Models in Mixed-Signal Flows

Paul Foster

The creation of behavioral models is only one part of the process of using those models in a mixed-signal design verification flow. If the model and design don't match, the effort is worthless. Even worse, it can damage the entire design verification process.

"Why should I care about keeping my behavioral models and designs in synch ?"

The benefit of using a bottom-up behavioral model to improve…
- 6 Jul 2011
Verification: True Stories of Assertion Driven Simulation (ADS) in the Wild

TeamVerify

Ever since Assertion-Driven Simulation (ADS) became available, I have been working with customers to integrate ADS into their standard design and verification flow. Below are some true stories from my direct experience with ADS out in the wilds of Silicon Valley.
The very first use mode I helped a customer to put together is what I call "Integration Bring Up". This flow is very applicable to designs with standard…
- 4 Jul 2011
SoC and IP: Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon

archive

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's ASIC. The Cadence PCI Express 3.0 controller in the ASIC reference card was attached to a LeCroy Summit T3-16 analyzer and Summit Z3-16 exerciser platform to demonstrate the…
- 30 Jun 2011
Verification: Video: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System Realization

jvh3

My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers inside Cadence. Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production. In this interview on the floor of DAC 2011, Mike gives a brief snapshot of the migration to the Universal Verification Methodology (UVM) by customers and EDA…
- 29 Jun 2011

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