Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Whiteboard Wednesdays: Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 1

References4U

In this week's Whiteboard Wednesday, Tom Hackett explains neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here: https://ip.cadence.com/uploads/1213/neural-network-calculator-xlxs-zip

www.youtube.com/watch
- 28 Nov 2017
Breakfast Bytes: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper

Paul McLellan

CCIX (pronounced see-six) is the Cache Coherent Interconnect for Accelerators. I wrote about it in my post CCIX is Pronounced C6 and also when Cadence announced its collaboration with TSMC, Arm and Xilinx in Xilinx/Arm/Cadence/TSMC Announce Worl...
- 28 Nov 2017
RF Engineering: Measuring Rapid IP3

Jommy

In the world of analog design, IP3—the third order intercept point, is a known parameter that is used to measure the linearity in the radio frequency (RF) components. The extracted IP3 values are very essential to determine the operating power ...
- 27 Nov 2017
Breakfast Bytes: What's For Breakfast? Video Preview December 4th to 8th 2017

Paul McLellan

https://youtu.be/LcmP8GkqvEw Coming from outside on the Cadence campus (camera Sean) Monday: JUG: Formal Verification Signoff Tuesday: Supercomputers Wednesday: Advanced Packaging Delivers More than Moore Thursday: Greg Yeri...
- 27 Nov 2017
Breakfast Bytes: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets

Paul McLellan

Increasingly, a lot of SOCs contain multicore processors, multiple separate processors, accelerators, and high-performance DMA devices. They also have cache memories, memories local to a block or core, used to improve performance. This causes a big p...
- 27 Nov 2017
Digital Design: Cadence Modus DFT at International Test Conference 2017

Rob Knoth

While DAC is the focal point for the EDA industry, the test community travels in a slightly separate orbit. There are many conferences throughout the year, and around the globe, to help bridge the problems and solutions in academia and the industry....
- 22 Nov 2017
Verification: 26262 4U: Infineon and the Incisive Functional Safety Simulator

XTeam

Infineon and Cadence have a bit of a history: they’ve been working together on functional safety mechanisms for around two and a half years now, and Infineon has been using the entire Cadence verification suite since the nineties. Functional safety is a serious hurdle for the automotive industry, and with the rise of ADAS systems, the issues that face Cadence and Infineon are about to get a lot more complicated…
- 22 Nov 2017
Breakfast Bytes: What You See Isn't Always What You Get

Paul McLellan

I wrote earlier in the week, in my post The Alto—Forty Years On, about the origin of the term WYSIWYG (pronounced whizzy-wig if you didn't already know). Today, it's the day before a break so I traditionally write about something completely off...
- 22 Nov 2017
System, PCB, & Package Design : A Peek into the Future of Signal Integrity with Artificial Neural Networks

Sigrity

Imagine how great life could be if computers or robots can do all our tedious work and we get to enjoy life and work on the things that are meaningful to us, i.e. the first figure on our left. These aspirations are definitely the goals of many ...
- 21 Nov 2017
The India Circuit: Will Artificial Intelligence Take Over Art Forms?

Madhavi Rao

In February last year, San Francisco’s art lovers were treated to a new kind of exhibition. Titled, “DeepDream: The Art of Neural Networks” and held in the trendy Mission District, the art on display was otherworldly, strange, and p...
- 21 Nov 2017
Analog/Custom Design: Virtuosity: Organizing Waveform Families

Arja H

When plotting waveforms in Virtuoso Visualization and Analysis across sweeps you might want to group plots with the same values together, or display each corner in the same color etc. Of course, you can right-click on the plot and select Copy to or Move to and move the plots manually, but did you know there was an assistant to do this for you?
- 21 Nov 2017
Breakfast Bytes: The Alto—Forty Years On

Paul McLellan

I talked yesterday about the history of the Xerox PARC Alto machine, which is a computer from the 1970s that is still influencing your smartphone today. On December 10th, forty years to the day after the presentation of the Alto to Xerox management a...
- 21 Nov 2017
System, PCB, & Package Design : How Can I Assess Process Variation in My IC Package Design?

BillAcito

In a previous blog we talked about the IC Packaging Design Variant tool. As you recall, this tool extended and eased the practice of a designer creating one database that represented multiple configurations of the same general design. Rather than man...
- 20 Nov 2017
Breakfast Bytes: What's For Breakfast? Video Preview November 27th to December 1st 2017

Paul McLellan

https://youtu.be/AMMOBeri5E8 Coming from building 10 fussball table (camera Sean) Monday: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets Tuesday: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper Wednesday: Chips...
- 20 Nov 2017
Breakfast Bytes: The Alto: The Machine That Changed the World

Paul McLellan

The Machine That Changed the World is actually the title of a well-known book about the history of Toyota's lean manufacturing and the importance of the automobile industry (and is fascinating in its own right). Something that changed the wo...
- 20 Nov 2017
Breakfast Bytes: CASPA Fuses AI and Semiconductor

Paul McLellan

CASPA is the Chinese American Semiconductor Professional Association. Once a year they have their annual conference and dinner banquet. I ended up getting involved with them a few years ago when I stepped in with 24-hours' notice to moderate a pa...
- 17 Nov 2017
Academic Network: Cadence Academic Network Lead Institutions

Zaidan

Introduction Many suggestions were spinning around the globe, many ideas are being presented, many meetings are being made about how to strengthen customer relationship with the company, how to make the customer see that he is an active part in the c...
- 17 Nov 2017
The India Circuit: Would You Let Your Child Ride in an Autonomous Car?

Madhavi Rao

DVCon is one of the premier conferences WW for design and verification. The DVCon India show has grown significantly over the last 4 years of its existence and this year’s edition was as vibrant as previous years. Cadence’s Apurva Kalia g...
- 16 Nov 2017
Analog/Custom Design: Dealing with AOCVs in SRAMs

Priyab

Systems on Chip, or SoCs as they’re more commonly called, have become increasingly more complex, and incorporate a dizzying array of functionality to keep up with the evolving trends of technology. Today’s SoCs are humongous multi-billion-gate designs with huge memories to enable complex and high-performance functions that are executed on them. It is quite common to have about 40% of an SoC’s real estate used for Static…
- 16 Nov 2017
Breakfast Bytes: Foundry Roadmaps: Intel, Samsung

Paul McLellan

I definitely had cognitive dissonance at the ARM foundry talks at TechCon. The first thing was that the organizer of the sessions was Kelvin Low. Since he was the marketing guy for Samsung Foundry until summer before joining Arm as their VP of market...
- 16 Nov 2017
Verification: Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!

XTeam

Even today, gate-level simulation is still a major signoff step for most semiconductor projects. However, those simulations can take days or weeks to run. A bug that causes a rerun of a gate regression can push a tapeout for weeks—but help is on the way!

The app note for gate-level simulation (GLS) methodology was released on November 11, 2017. It aims to showcase new methods and simulator-use models that make GLS…
- 15 Nov 2017
Breakfast Bytes: What's For Breakfast? Video Preview November 20th to 22nd 2017

Paul McLellan

https://youtu.be/aLx0C8H6qt8 Coming from Second Harvest Food Bank, San Jose (camera Sean) Monday: The Alto: The Machine That Changed the World Tuesday: The Alto—Forty Years On Wednesday: What You See Isn't What You Get Thursday: Happy...
- 15 Nov 2017
Breakfast Bytes: IEDM Preview 2017

Paul McLellan

Every December is IEDM, the IEEE International Electron Devices Meeting (IEDM). This year it is the 63rd, which partially explains the odd name. When it started, an "electron device" was a vacuum tube (we call them valves in England) a...
- 15 Nov 2017
Whiteboard Wednesdays: Whiteboard Wednesdays - Simplifying Fault Injection Simulations for Functional Safety Verification

References4U

In this week's Whiteboard Wednesday, YJ Patil answers the "What", "Why", and "How" of fault injection simulations for automotive designs.

https://youtu.be/oSI-Omtggl8
- 14 Nov 2017
Breakfast Bytes: Jasper User Group 2017

Paul McLellan

This year's Jasper User Group (JUG) took place on 7th November. It was the 10th JUG, and the 4th since Jasper was acquired by Cadence. I consulted for Jasper before I worked for Cadence, and so I took the opportunity to turn up (straight from CDNLive...
- 14 Nov 2017

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.