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System, PCB, & Package Design : What's Good About Allegro PCB Editor CM Analysis Control? 16.6 Has a Few New Enhancements!

Jerry GenPart

Beginning with the 16.6 version of Allegro PCB Editor, you can now toggle the Analysis flag directly from the Constraint Manager (CM) column header without using the “Analysis Modes” dialog.

Read on for more details …

The Constraint Manager column’s header is colored in yellow in case the related Analysis is set to OFF.
Here is a screenshot from the Electrical Worksheet > Net > Routing > Wiring…
- 3 Feb 2014
Verification: Covering Edges (part II)—“Inverse Normal” Distribution

teamspecman

In the previous example, we used the "select edge" to generate edge values for fields. But in many cases, what you really want to generate is not the exact edge, but "near the edges". For example, for a field of type uint (bits : 24), generate many items whose values are 0..4, and many of 0xfffff0..0xffffff. To achieve this, you can call this "the inverse normal distribution" and give more weight to the edges.…
- 29 Jan 2014
Whiteboard Wednesdays: Whiteboard Wednesdays - Closing the Memory Wall Gap

References4U

We're excited to introduce Whiteboard Wednesdays, a new video blog series that will shed some light and provide some practical insights on how to address a variety of intellectual property (IP-) related design challenges. Our inaugural segment addresses the memory wall gap--that phenomenon that occurs when the bandwidth of microprocessors outpaces the bandwidth of the memory in the design, degrading system performance…
- 21 Jan 2014
System, PCB, & Package Design : What's Good About Allegro PCB Editor New Ratsnest Display Option? Check Out 16.6!

Jerry GenPart

The 16.6 Allegro PCB Editor release has a ratsnest display option that is designed to reduce the density of rat display in the workspace. Rats seen as pass-through, ones not terminating to a pin in view, are automatically filtered from the display.

Read on for more details …

1. Enable the new rat display option by selecting Display > Show Rats > End in View Only.
2. This feature will make much more of an impact…
- 21 Jan 2014
Verification: ADI Success Verifying SoC Reset Using X-Propagation Technology - Video

Adam Sherer

Analog Devices Inc. succeeded in both speeding up the simulation and debug productivity for verifying SoC reset. In November 2013 at CDNLive India they presented a paper detailnig the new technology they applied to reset verification and eight bugs they found during the project. We were able to catch up with Sri Ranganayakulu just after his presentation and captured this video explaining the key points in his paper.
Sri had…
- 19 Jan 2014
Analog/Custom Design: Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Support

stacyw

With this month's title, I'll need to start adding the year, as this marks the one-year anniversary of the montly series. I know it's been a useful monthly exercise for me. Hopefully it has been helpful for everyone out there as well.
Application Notes
1. How to Utilize a Windowing Technique for Accurate DFT
Explains the best way to set up a transient simulation in ADE in order to achieve good results when performing…
- 17 Jan 2014
System, PCB, & Package Design : See the Differences Between Your Designs Visually with the Layer Compare Toolset in 16.6 APD and SiP Layout Tools

Jeff Gallagher

Have you ever wondered exactly what has changed between two different versions of a package substrate? Perhaps you've wanted to see exactly what metal on the top surface of your package is exposed through the combination of solder mask openings a...
- 15 Jan 2014
Verification: Recap of Another Successful Japan C-to-Silicon User Seminar

Jack Erickson

Back in November, our Japan office hosted a C-to-Silicon Compiler user meeting. They host about two per year, and the meetings have been growing in size and content. The November session drew 44 customers, representing 13 companies. The content spann...
- 13 Jan 2014
Digital Design: Five-Minute Tutorial: Start the New Year with Voltus

Kari

Happy New Year to all of our Digital Implementation Blog readers - and also to anyone new who is stopping by to check us out. We're glad you're here and we hope you'll hang out with us for a while!

I thought we could start this new year with one of Cadence's newest tools: Voltus IC Power Integrity Solution. You can read all the official details in this news article, but if you're a digital designer like…
- 9 Jan 2014
System, PCB, & Package Design : What's Good About AMS Multi-Core Engine Support? It’s in the 16.6 Release!

Jerry GenPart

The 16.6 AMS Simulator (PSpice) release now includes support for multi-core capabilities. There are several runtime options available to enhance the performance of simulation runs.

Read on for more details…

Performance of multi-core capabilties is enabled. There are focused performance enhancements for large designs with complex model instances like MOSFETS and BJT. In addition, I/O performance improvements with…
- 8 Jan 2014
System, PCB, & Package Design : Customer Support Recommended - Implementing Jumpers in Allegro PCB Editor

Naveen

Over the time, jumpers have found their importance in multiple applications. The following blog is aimed to provide more insight on their usage and implementation using Cadence Allegro PCB Editor.
What is a jumper? A wire jumper is typically a short wire used to electrically connect two points. On occasion, a wire jumper is necessary on a single-sided PCB to continue the signal connection over a group of etch traces. The…
- 7 Jan 2014
Verification: New Capabilities in the C-to-Silicon Compiler 2013 Releases

Jack Erickson

2013 was a banner year for high-level synthesis and C-to-Silicon Compiler in particular. We saw our customers take on over 75 new projects using C-to-Silicon, much of that coming from expanded adoption within our existing customers. These designs spa...
- 6 Jan 2014
RF Engineering: Have You Tried the New Transmission Line Library (rfTlineLib)?

Tawna

Happy New Year!

Have you tried the new Transmission Line Library (rfTlineLib) yet?

In case you missed it, rfTlineLib was introduced in IC 6.1.6 ISR1 plus MMSIM 12.1.1 -or- MMSIM13.1.

You may wonder....Why should I use the new rfTlineLib ? Well.....here...
- 3 Jan 2014
Analog/Custom Design: Virtuosity: 12 Things I Learned in November by Browsing Cadence Online Support

stacyw

New content on a wide variety of topics in November.
Product Information
1. Cadence Online Support Release Highlights
Find out about all the new improvements which have been made to the Product Pages on COS.
2. PVE Release Mechanism Change Letter
Changes in the way the Physical Verification System (PVS), QRC Extraction and K2 products are released.
Application Notes
3. Troubleshooting connect module issues with the AMS Designer…
- 18 Dec 2013
RF Engineering: SpectreRF Tutorials and Appnotes... Shhhh... We Have a NEW Best Kept Secret!

Tawna
It's been a while since you've heard from me...it has been a busy year for sure. One of the reasons I've been so quiet is that I was part of a team working diligently on our latest best kept secret:

The MMSIM 12.1.1/MMSIM 13.1 Documentation...
- 17 Dec 2013
Verification: Practical Guide to the UVM for $15 - Virginia, There is a Santa!

Adam Sherer

Wondering what to get the verification engineer on your list? You know, the one with the zealous love of SystemVerilog and UVM? It's the Practical Guide to Adopting the UVM, Second Edition for only $15!
The Practival Guide to the UVM is the most popular source of knowledge for the UVM. The second edition, available since the beginning of 2013, has sold over 3500 copies. Authored by Kathleen Meade and Sharon Rosenbeg…
- 13 Dec 2013
Analog/Custom Design: Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL

DeveshJain

Why is There a Need for Low Power Solutions?

With an increase in the demand for high-performance, multi-tasking systems-on-chips (SoCs) for communication and computing, the power requirements for these electronic chips have also greatly increased. There has been a surge in the production of portable devices like mobile phones, laptops, tablets, and game boxes that support multiple applications and use various multimedia…
- 10 Dec 2013
System, PCB, & Package Design : Take Your Via Structures from Ordinary to Exceptional with 16.6 IC Packaging Advanced Commands

Jeff Gallagher

Via structures—those reusable patterns of conductor clines and vias designers rely on to maximize their productivity—have a long-standing place in the robust escape routing feature set in the Cadence IC Packaging Tools. Many of us ...
- 5 Dec 2013
SoC and IP: Great Progress with Ethernet Standards Development

ArthurM

The IEEE 802 local area networking standards committee held its plenary meeting in Dallas recently at the Hyatt Regency Hotel. As a historical side, here is a photograph of the Hyatt from Dealey Plaza, the site of Kennedy’s assassination 50 years ago, and also a photograph of the old Texas school book depository from where the shots were fired:

I attended the 802.3 meetings and there was much progress with…
- 2 Dec 2013
Verification: Covering Edges (Part I) – Cool Automation

teamspecman

With random generation, most of the fields are due to be quite well covered. If the field is of a type with a wide space, e.g. address is of 32 bits, then most likely not each and every of the 0xffffffff values will be generated. As verification engineers, we know that bugs tend to hide in the edges. That is - what will happen if the transfer is sent to the last address, to 0xffffffff? The verification environment…
- 2 Dec 2013
Analog/Custom Design: SKILL for the Skilled: SKILL++ hi App Forms

Team SKILL

One way to learn how to use the SKILL++ Object System is by extending an application which already exists. Once you understand how extension by inheritance works, it will be easier to implement SKILL++ applications from the ground up. I.e., if you understand inheritance, you can better architect your application to prepare for it.
This episode of SKILL for the Skilled starts with an existing SKILL++ GUI application…
- 1 Dec 2013
Verification: Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit

SumeetAggarwal

Code coverage is an effective tool in the verification process, giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a very time-c...
- 25 Nov 2013
System, PCB, & Package Design : Optimize Your PCB Decoupling Capacitors and Remain a Person of Integrity

TeamAllegro

How much integrity is too much? If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are also more expensive than necessary and your decap mounting structures have vias in areas that could be better applied for signal routing. If you reduce the number of decaps, will you have less integrity? Will your PCB's Power…
- 22 Nov 2013
Analog/Custom Design: SKILL for the Skilled: Simple Testing Macros

Team SKILL

In this post I want to look at an easy way to write simple self-testing code. This includes using the SKILL built-in assert macro and a few other macros which you can derive from it. The assert macro This new macro, assert, was added to SKILL in SKILL version 32. You can find out which version of SKILL you are using with the SKILL function getSkillVersion, which returns a string such as "SKILL32.00"…
- 21 Nov 2013
Verification: High-Level Synthesis Now Spans the Datapath-Control Spectrum

Jack Erickson

When we talk to prospective high-level synthesis (HLS) customers, one of the slides we show is a pie chart that breaks down the types of production designs (that we are aware of) for which customers have used C-to-Silicon Compiler. The current snapsh...
- 20 Nov 2013

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