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Sarmad Dahir of Ericsson switched from directed testing to constrained-random test generation and the metric-driven verification (MDV) flow. Constrained-random testing is much more efficient than the old directed test approach, Dahir said. "Random testing makes things easier, because you won't have to target every possible scenario."

This translates into a time savings -- perhaps 30 percent for the overall…

Just a very quick post this week on a simple, but elegant new SPB16.3 feature for the Allegro Design Entry HDL product.

Prior to the SPB16.3 release, Design Entry HDL (DEHDL) did not have the capability of drawing a new wire from an anchor point of an existing wire. Introducing the anchor point wire stretch will give an extra ease of use factor to the way the wires are connected in the schematic.

You can stretch a wire…

Hi All,

An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code.  Templates can be used anywhere a user would like to create a single re-useable object that might operate on different data types.  An example would be to create a scoreboard (if you were not already using the ovm_scbd package…

Don't let the name CDNLive! confuse you.  It's the Cadence user's group conference and for North America this year it's occurring in Silicon Valley October 26th, 2010.  The conference also includes Technology Demos and a Designer Expo, but the heart of the event is really the user presentations.  If you haven't submitted a paper for consideration or haven't even thought of a topic to talk about, don't worry…

As a member of the EDA community, I find it interesting and somewhat frustrating to see how much we copy each other at times. Ever notice how one company might make a position on something, and once their message resonates, then a lot of other companies come out of the woodwork with me-too messaging and positioning?

I saw this happen on mixed-signal design, and now see it happening on signoff analysis.

Here at Cadence,…

• “Experts in SystemVerilog/Specman/VERA/System C”
• “Think Verification”
• “HVL (SystemC/C++/Verilog /Vera/Specman) Experts” 

While we tweet verification-related posts whenever we come across them, if you’re on LinkedIn…

In my last post, I left you in suspense, with your mouse hovering over the words "Click to add test" in ADE XL.  Clicking on this button will bring up the ADE XL Test Editor window (which should look suspiciously familiar) and a dialog asking you to point to the design you want to use.  This design does not have to be the same cellview as the adexl view you're working with.  It can be any design you want to…

With the SPB16.3 release of PCB SI, the Model Editor has been added to allow you to view, update, and check the syntax and data integrity for various models. The first release of the model editor contains simple functions. More utilities, tools, and features will be added in future releases. 

The Model Editor is a standalone executable and can be invoked in the console. The command line syntax is:

modeleditor –v –t title…

As my colleagues Adam Sherer and Joe Hupcey reported last week, Cadence has just published "A Practical Guide to Adopting the Universal Verification Methodology (UVM).” It is the world’s first book on the UVM. Or is it? The definition of "book" has become rather fuzzy these days. Could the UVM Reference Manual and User Guide published in PDF form by Accellera qualify as books? Would we still say that we had "published…

There are several ways that Incisive Formal Verifier (IFV) can be set to evaluate properties in parallel. The bottom line is that customers using these “productivity flows” have been dramatically increasing their verification throughput – turning days into hours, and hours into minutes.  In one customer case, what had been a 6 day run came in under 4 hours using this capability – a throughput improvement…

The Allegro Global Route Environment (GRE) has expanded its capabilities in the area of bundled editing in the SPB16.3 release.

It’s now easier to copy, move, and split bundles.

Copy Flow lets you copy the flow path from one bundle to another. Its primary goal is to allow faster creation of the designer’s flow plan. If you have repeated circuits or regions of your design that have a large number of bundles that will…

I know, it's been a long time since my last post.  You see, we've finally arrived at a topic near and dear to my heart -- ADE XL.  The reason for my hesitation in approaching this topic is not that it's difficult, but rather that there's so much to talk about that it's hard to know where to start.  It's a bit like trying to write a guidebook for the Louvre.  The place is enormous.  Do you describe the…