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Digital Design: Programmatically Capturing Cell Delay In The Encounter Digital Implementation System

BobD

A while back we were talking about how to programatically troubleshoot timing violations in Encounter. That post recieved a lot of good comments (thanks!) but one in particular touched on a point that I've worked on with other users, so I thought to raise it up for visibility here and go more in depth on the topic. Nataraja G asks:
"how can we get the delay values associated with that cell ? is it possible!"…
- 23 Jul 2010
SoC and IP: Micron provides detailed synopses of its NAND Flash and PCM presentations at Flash Memory Summit

archive

Micron has done a very smart thing (note to marketers: take matters into your own hands!) and has posted detailed summaries of all the technical presentations its people will be making at next month’s Flash Memory Summit (August 17-19). All of these presentations but one are about NAND Flash semiconductor memory. One is about PCM (Phase change Memory). I am shamelessly reproducing the summaries here:

Micron Keynote…
- 23 Jul 2010
SoC and IP: MemCon 2010: DDR3 1GHz and Beyond--Preregistered attendance now approaching 800. The end is near.

archive

Yesterday, preregistration attendance for MemCon 2010 jumped the 600 threshold. Today, it’s fast approaching 800 with about a registration coming in every minute or two. I guess everyone was waiting for the 1-week-to-go warning bell. In any case, I’m not sure we’ve ever tried to cram that many people in the room. On the other hand, there sure are some excellent networking opportunities to be had among this bunch of attendees…
- 22 Jul 2010
SoC and IP: Add PNY to the growing list of memory module vendors entering the SSD fray

archive

Memory-module vendor PNY has just announced its Optima line of 2.5-inch SSDs with SATA II (3 Gbps) interfaces available in 64- and 128-Gbyte capacities and listing at retail for $199.99 and $349.99 respectively. Sequential read/write speed for the 64-Gbyte Optima drive is spec’ed at 220 (read) and 100 (write) Mbytes/sec. Sequential read/write speed for the 128-Gbyte Optima drive is spec’ed at 235 (read) and 150 (write…
- 22 Jul 2010
Verification: Video Interview: UVM Book Authors Sharon Rosenberg And Kathleen Meade

jvh3

Earlier today a new book called "A Practical Guide to Adopting the Universal Verification Methodology (UVM)" was released. As a complement to this detailed post on the book, I've interviewed its authors, Sharon Rosenberg and Kathleen Meade. In this video, find out from the Sharon and Kathleen how they've worked to build upon the wealth of reference material already available for UVM (like the open source…
- 21 Jul 2010
SoC and IP: One Week Left: MemCon registration zooms past 600 attendees. Theme: DDR3 - 1 GHz and Beyond

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You have only one more week to sign up for MemCon 2010! It’s the one day this year you’ll hear everything you need to know about DDR SDRAM. This year’s MemCon focuses on fast SDRAM, which is a key system component in servers, PCs, notebooks, netbooks, tablets, pads, and embedded systems. Oh, and mobile phones too. SDRAMs cross all design borders: power, price, performance, processor architecture, multicore, many core…
- 21 Jul 2010
Verification: System Realization Alliance -- An Industry Collaboration

Steve Brown

System Realization is a very broad topic. It encompasses all aspects of system design, from chips to chassis. In particular, innovations in software are driving changes in the value chain, as highlighted in the EDA360 industry vision document. In ...
- 21 Jul 2010
Verification: New UVM Book Is For You And U But Not Ewe

Adam Sherer

A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the first book published on the emerging Accellera UVM. Written by the main authors of the user guide in the UVM release, this book provides more details and extends the methodology to address system level challenges. Unlike some books about earlier methodologies, it never assumes verification engineers are sheep that can only follow simple…
- 21 Jul 2010
SoC and IP: Wondering about mobile and consumer design and SPMT memory? Here’s your chance to learn about it, free. Free food and drink too!

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This blog has discussed an up-and-coming serial memory-interface technology called SPMT and you now have a chance to spend a couple of hours learning about it firsthand, for free. The Santa Clara chapter of the IEEE’s Consumer Electronics Society is sponsoring an evening panel discussion on Tuesday, July 27, which is the night before MemCon 2010.

Jim Venable, President of the SPMT Consortium and Dr. Sehat Sutardja…
- 20 Jul 2010
SoC and IP: Intel X-25M 80GB SSD Performance after 45 days of use: Time ain’t on my side, no it’s not.

archive

A member of Overclock.Net going by the handle Kiggold just posted two screen shots from HD Tune Pro 3.00 showing the throughput of an Intel X-25M 80GB SSD when new and after 45 days. When new, the drive took a little time to come up to speed and then stabilized at an average transfer rate of 233 Mbytes/sec. After 45 days, HD Tune Pro shows that the SSD’s average transfer rate has dropped to 226 Mbytes/sec, which is a…
- 19 Jul 2010
SoC and IP: DDR3 power savings may be more important for Embedded Apps than for PCs

archive

A new hands-on article written by Patrick Schmid and Achim Roos just appeared on the Tom’s Hardware site (“How Much Power Does Low-Voltage DDR3 Memory Really Save?”). The article takes an in-depth, real-world look at 1.35/1.25V DDR3 SDRAM power consumption versus DDR2 SDRAM power consumption in a PC environment. Here’s the meat of the conclusion:

“There are more interesting differences in power consumption, though…
- 19 Jul 2010
Verification: Sign Up For Free Verification Sessions -- Only A Few Days Left

teamspecman

Mark your calendar and sign up for the two upcoming free verification sessions sponsored by Cadence. Space is limited. So, please sign up today!
JULY 21^st
All-Day, Hands-on technical workshop in Irvine, CA
Topic: Advanced Verification Techniques using e/SV Workshop
Learn how to architect an advanced testbench using OVM/UVM that contains generation, coverage and checking and much, much more.....
This workshop will focus on…
- 19 Jul 2010
Verification: Software Development Tool Teardown For The Motorola Droid

jasona

Lately, device teardowns of consumer electronics have become popular. There are many articles and videos showing what's inside a particular device. EE Times even had an article asking if they were useful and who actually benefits from them (...
- 19 Jul 2010
Verification: More Thoughts On How To Choose Between The OVM And The UVM

tomacadence

There has been a lot of on-line discussion since DAC about whether the Universal Verification Methodology (UVM) is ready for prime time. My last three blog posts (1 - 2 - 3) addressed some of the reasons why I strongly believe that the UVM is ready and why you should consider it for your next verification project.
In the middle of my series, Mark Glasser from Mentor posted in his blog that "Eventually there will be a tipping…
- 16 Jul 2010
SoC and IP: AnandTech analyzes Crucial C300 SSD with Marvell controller in “The SSD Diaries.” You must read these conclusions.

archive

Anand Lal Shimpi, the man behind the AnandTech.com Web site, has published an extended review of Crucial’s C300 SSD. Two things that make the Crucial C300 SSD somewhat unique are the use of a Marvell SSD controller chip paired with Crucial’s home-grown firmware. The online article is worthwhile for its extensive charts showing drive performance. You should know that the Crucial C300 drive performs pretty well. AnandTech…
- 14 Jul 2010
Verification: Changing the Status Quo in SoC to System Hand-off

jasona

As part of EDA360 Cadence is learning how to play a more significant role in the SoC-to-System handoff. To date, Cadence has served the SoC market by enabling companies to design and verify faster, bigger, and better SoC devices that get used by thei...
- 13 Jul 2010
SoC and IP: MemCon 2010 looms (July 28). Huge networking opportunity with big list of attendees from movers and shakers in the semiconductor memory industry.

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Memcon 2010 is a little more than two weeks away and although we’ve blogged about the terrific keynotes, presentations, and panels that will take place, we haven’t really discussed the immense networking opportunity that’s also part of the event. A huge number of attendees from memory vendors, system vendors, and research firms are attending this year and July 28 at MemCon 2010 may be the only chance you’ll get all year…
- 12 Jul 2010
SoC and IP: Upgrading Old PCs with SSDs: Where’s the Notion of Balance?

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Martin Veitch of the UK’s www.CIO.co.uk online magazine recently wrote a blog that echoes one SSD vendor’s push to get SSDs considered as serious upgrades for aging PCs. This SSD vendor is trying to draft behind the top PC upgrade, more RAM, which is commonly known to boost PC performance--up to a point. Veitch quotes the vendor’s vice president for SSD and Flash: "The hard drive is the bottleneck." Yes, well maybe it…
- 9 Jul 2010
SoC and IP: SSDs in embedded control: cold rolling steel in old European factories, Part 2, now with photos

archive

Back in May, the Denali Memory Report covered an industrial application for SSDs involving a European steel mill. The SSD-based control system was designed and implemented by Christian Lequeux of CL Consulting in Belgium. Monsieur Lequeux was kind enough to send some really interesting photos and some additional explanation. He writes that the SSDs were ideal for this application because the control system sits in an…
- 8 Jul 2010
SoC and IP: Flash Memory Summit looms in August: All things Flash

archive

When we weren’t looking, registration for MemCon zoomed past 500 and it’s still climbing. (Register here.) This year MemCon is focusing on DRAM and if you need to know about Flash as well, this is indeed your lucky year. The Flash Memory Summit takes place at the Santa Clara Convention Center in August, from the 17th to the 19th. This event is the only conference in the world focused exclusively on Flash memory and its…
- 8 Jul 2010
SoC and IP: Virident PCIe SSD delivers 320,000 read IOPS with 24-year service life

archive

Add Virident to the growing list of companies that have introduced SSDs in the form of PCIe expansion cards to achieve higher storage throughput. The company’s just-introduced tachIOn Drive delivers 200,000 4-kbyte read/write IOPS for 75/25% read/write workloads. The SSD board incorporates a fan-cooled Flash controller and eight Flash modules to create a 200-Gbyte SSD. The Flash modules can be stacked and the board accommodates…
- 7 Jul 2010
Verification: Why The UVM Is Ready For Production Use Today -- Part 3

tomacadence

This is the final installment of my blog posts based on the three common questions I heard at DAC regarding the Universal Verification Methodology (UVM). I've already answered the questions "What does the UVM mean for the future of the OVM and VMM?" and "Why is the first release of the UVM labelled as "Early Adopter (EA)?"
The third and final question that I'd like to address is "Will there…
- 7 Jul 2010
Verification: Duolog Interview At DAC 2010, And The IP Integration Aspect Of EDA360

jvh3

One virtue of events like DAC is that is provides an open forum for vendors to show how they crystallize high-level, abstract ideas to concrete, valuable products. Cadence Connections program partner Duolog made the most of this opportunity by exhibiting their "Socrates" chip integration platform for addressing the growing problem of integrating IP of all shapes, sizes, and domains -- plus maintaining all the…
- 7 Jul 2010
SoC and IP: Specialty semiconductor foundry TowerJazz licenses “Y-Flash” IP to “leading” digital foundry

archive

TowerJazz, the specialty semiconductor foundry created by the merger of Tower Semiconductor and Jazz Semiconductor in 2008, has announced that it has licensed its “Y-Flash” MTP (multiple-times programmable) CMOS memory IP to an unnamed, “leading” digital foundry. TowerJazz’s Y-Flash IP creates a Flash memory cell with standard CMOS processing. In other words, the Y-Flash memory cell has only one gate and it’s a floating…
- 6 Jul 2010
System, PCB, & Package Design : What's Good About Via DRCs In Allegro Constraint Manager? It's In SPB16.3!

Jerry GenPart

Current design technologies require extremely tight matching requirements right down to the overall net topologies to ensure that any deviations in propagation delays are minimized. As a result, design guidelines call for matching the number of vias for a group of signals. The prior releases of Constraint Manager support a "MAX_VIA_COUNT" constraint which does not meet the needs of these new design requirements. The SPB16…
- 2 Jul 2010

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