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Today’s high-performance electronic systems are being driven by ever-increasing complexity and density, requiring designers to consider EMI and EMC, as well as PI/SI and high-speed RF/microwave issues. To accelerate the design process and meet aggressive delivery schedules, engineers need to be able to perform EM cross-fabric and multiphysics analysis to model, simulate, and analyze these effects on chip, package, and…

The Cadence VIP portfolio is used to provide various standard protocol VIPs for testing the DUT with respective protocol interfaces. All these VIPs are released together as VIPCAT release, which is called the VIP catalog. Since these fully tested VIPs are readily available, they will play a main role in reducing the time to market for the customer DUTs.

Cadence follows consistent architecture for all its VIPs and ensures…

In the dynamic realm of system design, ensuring signals arrive unscathed at their destinations is just the tip of the iceberg. The intricacies evolve with escalating package densities, finer PCB traces, and soaring frequencies, requiring a synergy of electrical, mechanical, electromagnetic, and thermal dynamics. The growing complexities and niceties unveil the need for optimal performance, a reliable process where human…

The purpose of the verification plan, or vplan as we call it, is to capture all the verification goals needed to prove that the device works as specified.  It’s a big responsibility! Getting it right means having a good blueprint for verification closure. However, getting it wrong could result in bug escapes, wasting of resources, and possibly leading to a device failing altogether. In fact, verification planning…

Power integrity is becoming one of the most pressing challenges at advanced nodes, with designers regularly facing a significant number of EMIR violations at signoff.

In this era of pervasive data, hyper-connectivity, and artificial intelligence, design size is constantly increasing, and the popularity of 3D-IC design is adding another dimension to power integrity complexity.

To overcome those challenges, it is imperative…

Maintaining connectivity during custom layout creation enables key capabilities of Cadence’s custom layout flow. This helps you accurately predict and optimize the performance of your circuits—significantly boosting your layout productivity.

Virtuoso Studio’s custom design solution has new features that let you preserve the connectivity of virtually all custom designs.

Join Cadence Training and Sr…

As we welcome 2024 now we will not miss to look back at our most-viewed blogs of the year and give an overview what else happened in our world of Education throughout the year.

During 2023 we published 6 more Training Blogs to keep you up to date with new and enhanced features around System Design and Verification.

We were also able to publish 2 Webinar recordings that you can find here:

Solve Tricky SVA Problems with…