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Breakfast Bytes: What's For Breakfast? Video Preview March 5th to March 9th 2018

Paul McLellan

https://youtu.be/YesJPmKCeio Coming from Embedded World, Nuremberg (camera Robert Schweiger) Monday: Spectre with a Red Hat Tuesday: Spectre with a Red Hat 2 Wednesday: Embedded World Keynotes Thursday: Cadence and ime...
- 1 Mar 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Unpacking the DFI Low-Power Interface

References4U

In this week's Whiteboard Wednesday, John MacLaren describes the operation of the DFI Low Power Interface to reduce PHY power consumption.

www.youtube.com/watch
- 27 Feb 2018
Breakfast Bytes: Embedded World 2018: Dreaming of Electric Cars

Paul McLellan

I am at embedded world in Nuremberg. One thing that is not here is warm weather. All that I can say is that it is warmer in Nuremberg than Munich, -7ºC instead of -11ºC. People don't remember it being this cold for many years (although ...
- 27 Feb 2018
SoC and IP: Why Software-Based GPS Is Great for Location-Based IoT Applications

PaulaJones

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo of a software-based GPS receiver from Galileo Satellite Navigation running off a Cadence Tensilica Fusion F1 DSP. It’s a very impressive demo—come by...
- 27 Feb 2018
Breakfast Bytes: How Many Journalists per Square Acre?

Paul McLellan

It doesn't matter how low your standard is for science journalism, the journalists always seem to manage to go lower. I realize that the sort of people who go to journalism school tend not to be the most scientific. In fact, given the employment ...
- 27 Feb 2018
Analog/Custom Design: Take Advantage of Advancements in Real Number Modeling and Simulation

msteam

Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor…
- 26 Feb 2018
Verification: Xcelium and Cavium: What’s the Deal?

XTeam

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers now. While that’s all well and good, why is it such a big deal? Well, Cadence gathered up Ziv Binyamini, Gopal Hegde, and Ann Keffer to answer just that question in a video:

https://youtu.be/QTN6goFWWBo

What does it mean that Xcelium is now available on Cavium’s Thunder X2 servers? Well, the Thunder X2 brings a lot of advantages…
- 26 Feb 2018
Breakfast Bytes: Patents: Licensed by the Ton

Paul McLellan

I wrote recently about What Happens in a Patent Lawsuit? Today, I want to look at patents from a higher level: why do we have them, and how well do they work in the semiconductor and EDA industries. The Patent Tradeoff The basic “tradeoff&rdquo...
- 26 Feb 2018
SoC and IP: Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

tomhackett

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers are currently in transit around the world? It turns out that no one knows for sure, but the best guess is that there are about 20 million containers in service today. And it's a safe bet that those containers are carrying…
- 23 Feb 2018
Breakfast Bytes: How Do You Get to Be CEO?

Paul McLellan

I wrote last week about Being CEO and I said that I'd done it twice in my career. But I omitted an important point: how do you get to be CEO? I assume we are talking about a small company, or a startup. But, in fact, a private equity firm f...
- 23 Feb 2018
Analog/Custom Design: Virtuosity: New Eye Diagram Measurements

Arja H

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create eye diagrams, add masks and also calculate some standard measurements. The measurements have recently been enhanced by adding more jitter calculations, maximum eye height and width calculations, level annotations and Bit Error Rate (BER) curves.
- 23 Feb 2018
Verification: New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

DimitryP

As discussed in the previous installment of this blog, a new class of atomic transactions was introduced in the AMBA® 5 ACE/AXI specification to make operations at the remote locations more streamlined and efficient. We have considered an example of AtomicStore transaction with ADD operation and discussed why it was more efficient than relying on the older semaphore-like exclusive operations. In this installment of…
- 22 Feb 2018
Breakfast Bytes: What's For Breakfast? Video Preview February 26th to March 2nd 2018

Paul McLellan

https://youtu.be/wq86edcqTdw Coming from Building 10 lobby (camera Sean) Monday: Patents Licensed by the Ton Tuesday: How Many Journalists per Square Acre Wednesday: embedded world Thursday: What the FEC is Forward Error Co...
- 22 Feb 2018
System, PCB, & Package Design : SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)

Sigrity

Backchannel Training Another capability related to equalization adaptation is backchannel training. Many high speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide i...
- 22 Feb 2018
Breakfast Bytes: Paul Kocher: Differential Power Analysis and Spectre

Paul McLellan

Paul Kocher is a legend in security. A couple of weeks ago SiFive hosted a seminar by Paul. They do these regularly, usually on a small scale, but this one required a large conference room in the San Mateo Marriott across from their offices. Ev...
- 22 Feb 2018
Digital Design: Wind of Change in Hardware Design

dpursley

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I stepped out of the office yesterday. While I’m sure it will be cold again by the time this blog gets published, yesterday made me think about how things are changing.

In the 2017 annual HLS survey, we confirmed that wireless is the fastest growing market segment for high-level synthesis (HLS). That wasn’t much of a surprise, because…
- 21 Feb 2018
Breakfast Bytes: Is Big Brother Watching You?

Paul McLellan

I recently came across a fascinating piece by Paramal Satyal. He is Nepalese although these days he seems to live in France. His piece is largely autobiographical, but what caught my eye was a bit in the middle where he looks at one of the most ...
- 21 Feb 2018
Verification: Coming to DVCon? It's Not Too Late to Sign Up!

XTeam

Are you coming to DVCon this year? It’s right around the corner, but it’s not too late to register! DVCon is the flagship conference for all things functional design and verification, showcasing the freshest technologies, techniques, tips, and tricks.

Cadence will be in booth 702, bringing the newest tools and methodologies for working with complex silicon, SoCs, and systems. To check out the schedule, look…
- 20 Feb 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Using DDR PHY Power Features to Reduce Power Dissipation

References4U

In this week's Whiteboard Wednesday video, Marc Greenberg explains the ways to optimize power dissipation by controlling DDR PHY performance settings.

https://youtu.be/cNzggIZIhig
- 20 Feb 2018
Breakfast Bytes: embedded world 2018 Preview

Paul McLellan

It's nearly time for embedded world 2018 (yes, it likes to be trendy and put it all in lower-case), which takes place February 27 to March 1. It happens every year in Nuremberg, and is the biggest embedded conference in the world. Cadence will be the...
- 20 Feb 2018
Breakfast Bytes: Why 1 Is Not a Prime Number

Paul McLellan

It's Presidents' Day and Cadence is on holiday. So time for me to write about something that is interesting (well, it's interesting to me, anyway) but not directly anything to do with semiconductors or EDA. The Fundamental Theorem of Arithmetic Some...
- 19 Feb 2018
Breakfast Bytes: Suddenly You Are CEO. What Do You Do Next?

Paul McLellan

We've covered sales, marketing, and application engineering. Let's go up to the top, and look at what is involved in being CEO. Some aspects of the job generalize to other senior management jobs, but some aspects are unique. I do have some e...
- 16 Feb 2018
Breakfast Bytes: What's For Breakfast? Video Preview February 19th to 23rd 2018

Paul McLellan

https://youtu.be/M3p1Luf4mtk Coming from Guangzhou, China (camera Carey Guo) Monday: Why Is 1 Not a Prime Number Tuesday: embedded world Preview Wednesday: Is Big Brother Watching You? Thursday: Paul Kocher: Differential Power ...
- 15 Feb 2018
Breakfast Bytes: Zombies

Paul McLellan

What is a zombie? It depends on who you ask. Venture capitalists talk about zombies, and so do operating system programmers. Not to mention people who watch zombie movies. And in a surprise bit of news just a few weeks ago, a satellite thought to be ...
- 15 Feb 2018
Digital Design: Wondering How Moving To Advanced Nodes Might Affect Manufacturability And Yield?

Philippe Hurat

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose, CA) you can hear from experts in the field on how these challenges are being addressed. On Feb. 28 you can hear from AMD and Cadence on “Applying mac...
- 14 Feb 2018

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