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System, PCB, & Package Design : SI Methodology for Multi-Gigabit Serial Link Interfaces (3 of 8)

Sigrity

IBIS-AMI Modeling With initial PCB trace and via models in place for our hypothetical PCI Express Gen 4 serial link, the remaining missing piece is for an IBIS-AMI model of the transmitter, with “AMI” standing for Algorithmic Model Interf...
- 3 Jan 2018
Breakfast Bytes: Gary Patton on GF, IBM, 7nm, EUV, and More

Paul McLellan

At IEDM in December, I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to discuss their manufacturing in general, and especially their 7nm process, EUV, and their Malta fab8, where Gary is based. We actually met the day before the presentatio...
- 3 Jan 2018
The India Circuit: Face Recognition and Hackathon: An Unlikely and Innovative Combination

Madhavi Rao

Happy New Year! While most other folks are just easing back to work, those of us in the Indian semiconductor ecosystem are gearing up for one of our biggest events of the year. The first week of January is when the VLSI and Embedded Systems Conf...
- 3 Jan 2018
Breakfast Bytes: Intel 10nm

Paul McLellan

At IEDM last month, Intel announced details of their 10nm process. Later the same morning, they also gave details on a 22nm process, 22FFL, which is a second generation 22nm process (their first FinFET process was also 22nm) targeted at mobile and RF...
- 2 Jan 2018
Breakfast Bytes: Frankenstein

Paul McLellan

"Hail to thee, blithe spirit! Bird thou never wert"...and Frankenstein. What do these two have to do with each other? And why did I pick today to ask such an odd question? You may recognize the quote as the opening line of Percy Bysshe She...
- 1 Jan 2018
Breakfast Bytes: What's For Breakfast? Video Preview January 1st to 5th 2018

Paul McLellan

https://youtu.be/Xja6H1meqac Coming from Yosemite National Park (camera Carey Guo) Monday: Frankenstein Tuesday: Intel 10nm Wednesday: Gary Patton at IEDM Thursday: CES 2018 Preview Friday: GLOBALFOUNDRIES 7nm www.break...
- 29 Dec 2017
Breakfast Bytes: Why Don't Planes Obey Moore's Law?

Paul McLellan

In my post about Silexica (Silexica: Mastering Multicore) I said that I like to use planes as an analogy for cores in a multi-core system. As I said there: They haven't got appreciably faster but you can have lots of them. If you want to transp...
- 15 Dec 2017
Analog/Custom Design: Virtuosity: From Hatchlings to Fledglings to a Flock of Birds Blogging Together

Rishu Misri Jaggi

“The reason birds can fly and we can't is simply because they have perfect faith, for to have faith is to have wings.” ― J.M. Barrie, The Little White Bird When a few of us in the Cadence CAS Technical Communications Engi...
- 14 Dec 2017
Breakfast Bytes: Blue LEDs, Nobel Prizes, and IEDM Keynote

Paul McLellan

At IEDM last week, for the first time, there was a second plenary session (awards and keynotes) on Wednesday. presented by Nobel Laureate Hiroshi Amano, one of the inventors of the high intensity blue light emitting diode (LED). He ta...
- 14 Dec 2017
Breakfast Bytes: Ploughing 1 TB of RAM with Twenty x86 Oxen and 10,000 RISC-V Chickens

Paul McLellan

OK, that wins the prize for best title of a presentation in the recent RISC-V workshop, or pretty much any workshop. I couldn't resist using it aa a title for this post. Can you say click-bait? You'll have to read almost to the end ...
- 13 Dec 2017
Whiteboard Wednesdays: Whiteboard Wednesdays - What to expect from TLM 2.0 Models for Memory Subsystems - Part 1

References4U

In this week's Whiteboard Wednesday, Vivek Nandakumar explains the behavioral differences between Loosely Timed (LT) and Approximately Timed (AT) TLM 2.0 models.

https://youtu.be/TRdukWFeQSM
- 12 Dec 2017
Breakfast Bytes: RISC-V Workshop, Milpitas

Paul McLellan

The latest semi-annual RISC-V workshop took place the week after Thanksgiving. The last one was in Shanghai. The next one is in Barcelona. This one was in...Milpitas. At least it didn't require a plane to get there. It was at what I think of as S...
- 12 Dec 2017
Learning and Support: What's New in Cadence Help 3.0?

Vani V

I am sure you would agree when I say that a help tool is the one utility without which no software service can ever work. Cadence Help is one such powerful tool, which is integrated with almost all Cadence products; you would never realize that it is a separate application. It is available on all supported platforms and can be invoked from the Help menu or dialog boxes of your Cadence products.
- 12 Dec 2017
Breakfast Bytes: COTS? Commercial Products in US Government Electronics

Paul McLellan

COTS is government jargon for Commercial Off-The-Shelf. This means the government going out and purchasing commercial products that are available to anyone, not something commissioned specially by the government and unavailable to anyone else. It can...
- 11 Dec 2017
The India Circuit: Four Exciting Examples of Modern AI from NVIDIA

Madhavi Rao

A few months ago, we had the honor of having Vishal Dhupar, Managing Director of NVIDIA India, speak at an executive forum that we had in Bangalore. NVIDIA's GPU technology is used to power what they call "modern AI", so the audien...
- 11 Dec 2017
Analog/Custom Design: Virtuosity: SKILLful Virtuoso Visualization and Analysis

Ashu V

If you’re a SKILL enthusiast, you’ll be happy to know that the latest IC6.1.7 ISR release offers some very useful and handy SKILL functions to perform certain tasks in ViVA. You may find them useful too. Let’s take a quick look at them.
- 10 Dec 2017
Breakfast Bytes: IEDM 2017

Paul McLellan

The start of December means it is the International Electron Devices Meeting in San Francisco (it used to be in Washington alternate years but it is in San Francisco for the forseeable future). I have been here all week. Highlights were keynotes from...
- 8 Dec 2017
Analog/Custom Design: Virtuosity: Can I Graphically Edit Width Spacing Patterns?

KomalJohar

We have enhanced the editing modes available for WSPs. In addition to the text-based editing, you can now graphically edit WSPs in the preview mode.
- 7 Dec 2017
Academic Network: 2017 Workshop on Electronic Design Automation in Tainan Taiwan

Tracy Zhu

It was the third continuous year that Cadence Academic Network supported the Workshop on Electronic Design Automation (EDA) in Taiwan. The event was hosted by National Cheng Kung University in Tainan on December 2-3, 2017. &nb...
- 7 Dec 2017
Breakfast Bytes: Greg Yeric and Rob Aitken Dive into the Details

Paul McLellan

The last day of TechCon had two keynotes rich in deeper technical content, from Greg Yeric on Process Technology Limbo, and Rob Aitken, on How to Build and Connect a Trillion Things. Greg Yeric Greg is focused on what new technologies are going to be...
- 7 Dec 2017
Breakfast Bytes: Advanced Packaging Delivers More Than Moore

Paul McLellan

Moore's Law is running out of steam. Depending on your point of view, it is dead, dying or slowing. As a result, there is an increasing interest in technologies that go under the title "More than Moore", meaning ways of getting better ...
- 6 Dec 2017
Digital Design: Get Early Silicon Learning to Accelerate Yield Ramp-up

Philippe Hurat

How important is it for your advanced node products to get early silicon learning? How are your test chips compared to real products? Some answers are provided below in short summary from the “Methodology for Analyzing and Quantifying Des...
- 5 Dec 2017
Whiteboard Wednesdays: Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

References4U

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here: https://ip.cadence.com/uploads/1213/neural-network-calculator-xlxs-zip

https://youtu.be/ow1ZuOPD72I
- 5 Dec 2017
Analog/Custom Design: Virtuosity: Can I Plot Signals with Different Axis Units in the Same Window?

Arja H

Have you been frustrated trying to drag signals around in Virtuoso Visualization and Analysis only to see this icon telling you that you can't drag the signal there? You can right-click on the axis and check the Allow Any Units option,...
- 5 Dec 2017
Breakfast Bytes: Supercomputers

Paul McLellan

HPC, or high-performance computing, is one of the big focus areas for semiconductors (along with mobile, automotive and IoT). The highest performance computing of all are the supercomputers. Whereas the computers we have on our laptops, smartpho...
- 5 Dec 2017

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