Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Breakfast Bytes: Kaufman Award Dinner: The Tom Williams Story

Paul McLellan

Wednesday night it was the annual Kaufman Award Dinner to honor this year's recipient, Tom Williams. To learn more about the history of the award, read my post Who Was Phil Kaufman? I also talked to Tom Wiliams in Italy last month, when the ...
- 9 Nov 2018
Breakfast Bytes: RISC-V Summit Preview: Pascal or Linux?

Paul McLellan

Coming up in December, in the same week as IEDM, is the RISC-V Summit at the Santa Clara Convention Center. For a basic introduction to RISC-V see my post RISC-V—Instruction Sets Want to Be Free. It is clear that RISC-V is already bec...
- 8 Nov 2018
Breakfast Bytes: IEDM Preview: 3nm and More

Paul McLellan

A lot of aspects of EDA and semiconductor are fairly easy to predict: you read off the process roadmap for the big guys and work out the implications for tools, IP, and methodology. Of course, it is harder back away from the leading edge since t...
- 7 Nov 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - How the Cadence 112G SerDes IP Solves the Challenges of Long-Reach Signaling

References4U

In this week’s Whiteboard Wednesday, Wendy Wu explains what NRZ and PAM-4 signaling is all about and the sources of channel loss that make high-speed, long-reach SerDes design so challenging. She then describes the unique architectural advantages of the Cadence® 112G Long-Reach SerDes IP that makes it an ideal choice for high-speed networking and server chip designs.

https://youtu.be/s_kZBbbf110
- 6 Nov 2018
Breakfast Bytes: Automotive Summit: Driving an Industry with Electronics

Paul McLellan

Coming up on November 14th is the Cadence Automotive Summit. This will be held on the Cadence campus (2655 Seely Avenue, San Jose if you need a street adress for your map app). The day starts with registration and breakfast at 8.30am and wraps ...
- 6 Nov 2018
The India Circuit: A Diwali with Green Crackers and Cooking Bots

Madhavi Rao

It’s Diwali! My favorite festival out of all the many celebrations that we Indians have through the year. But Diwali nowadays is different from even just five years ago. I wrote last year about how there was a ban on lighting firecrackers (an i...
- 5 Nov 2018
Breakfast Bytes: Breakfast Buffet for October 2018

Paul McLellan

https://youtu.be/YBlBzB3n504 The three highlighted posts for October were: CDNLive Israel 2018 The World's First Working 7nm 112G Long Reach SerDes Silicon "Alexa, What Is HiFi 5?" Sign up for Sunday Brunch, the weekly Break...
- 5 Nov 2018
Breakfast Bytes: China Update

Paul McLellan

Over the last couple of weeks, I came across various little things about China, none of which justified a blog post all on their own, but it seems a good time to give an update on what's going on over there. I consider China to be the biggest story i...
- 5 Nov 2018
Breakfast Bytes: Sunday Brunch Video for 4th November 2018

Paul McLellan

https://youtu.be/HCJG-tABZWE Made at Linley Fall Processor Conference (camera Sean) Monday: Formal Signoff with JasperGold Tuesday: Texas Instruments on Automotive Reliability Wednesday: "Alexa, What is HiFi 5?" Thursday: Yoga is Pass&...
- 4 Nov 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之10：易于使用的改进

TeamAllegro

我所认识的大多数PCB设计工程师跟我有同样的习惯… 我们有最喜欢的颜色、板层名称、定制的键盘，我们最大的目标是看到一天之内完成了多少条网络布线。我们很少有改变这些使用习惯，—但当我们改变时，要么是因为换了设计人员，要么是由于这些证明是好的流程却不再满足工作要求，我们不得不改变。您能联想到吗？你们之中有幸参加之前Cadence用户大会CDNLive会议的，可能会记得，作为客户，我通常会演讲“Allegro技术小贴士-您知道吗？”平心而论，我被邀...
- 2 Nov 2018
Breakfast Bytes: ERI: OpenROAD

Paul McLellan

If I had to summarize DARPA's Electronic Resurgence Initiative in one phrase, it would be "getting the cost of design down." As I've said several times this week, the US Department of Defense (DoD) does not have high volumes an...
- 2 Nov 2018
Breakfast Bytes: Yoga is Passé, the Future Is CurvyCore

Paul McLellan

Despite CurvyCore sounding like something that you might take classes in at your local gym, it is actually new technology that allows computing and representing non-Manhattan shapes in Virtuoso. The CurvyCore technology is targeted at a wide range of...
- 1 Nov 2018
Breakfast Bytes: "Alexa, What Is HiFi 5?"

Paul McLellan

"Alexa, turn on the living room light." "Okay." "Alexa, what is Cadence announcing on Halloween morning?" "The Tensilica High Five! Yay." "Alexa, it's the Tensilica HiFi 5 DSP." "Okay." Audio Processing Way back in the past, audio process...
- 31 Oct 2018
Whiteboard Wednesdays: Whiteboard Wednesdays – Machines with Voice UI and Tensilica HiFi 5 DSP

References4U

In this week’s Whiteboard Wednesdays video, Sachin Ghanekar talks about the new Tensilica HiFi 5 DSP, the first DSP optimized for AI speech and audio processing. This fifth-generation HiFi DSP offers 2X audio processing and 4X neural network (NN) processing improvements versus its predecessor, making it ideal for voice-controlled user interfaces in digital home assistants and automotive infotainment.

www.youtube…
- 31 Oct 2018
Analog/Custom Design: Virtuosity: Is the Coloring Data Compliant with the MPT Flow?

KomalJohar

In advanced node designs, to help you create designs that are compliant with the Multi-Patterning (MPT) flow set up, we have introduced the methodology compliance checker on the Multi-Patterning toolbar.
- 31 Oct 2018
System, PCB, & Package Design : How Do I Know What Functionality to Put on Which PCB Board?

TeamAllegro

There’s only so much you can do with a single printed circuit board (PCB). We’ve seen advances in miniaturization and the steady rise in the number of transistors you can squeeze on a single chip.
- 30 Oct 2018
Breakfast Bytes: Texas Instruments on Automotive Reliability

Paul McLellan

Recently, I seem to have been running into people from Texas Instruments (TI) talking about various aspects of automotive reliability. I'm going to try and summarize three presentations that I attended in this post: Functional Safety Fault-Injection...
- 30 Oct 2018
Breakfast Bytes: Formal Signoff with JasperGold

Paul McLellan

At the recent Jasper User Group, I said that there were several themes. For overall coverage of the event, see my post Jasper User Group 2018. One was post-silicon debug, which I wrote about in the post Formal Post-Silicon Debug. Another theme w...
- 29 Oct 2018
Breakfast Bytes: Sunday Brunch Video for 28th October 2018

Paul McLellan

https://youtu.be/1vU3sg3QlWc Coming from building 8 lab (camera Sean) Monday: The World's First Working 7nm 112G Long Reach SerDes Silicon Tuesday: Arm TechCon: Get Ready for the NEOVERSE Wednesday: ERI: Hardware Security Work...
- 28 Oct 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之9：新设计规则检查

TeamAllegro

Allegro PCB 17.2-2016发行版增强了钻孔相关功能我们为实际的钻孔工具、背钻工具、方形孔、沉头孔等增加了焊盘定义，并增加了钻孔容差。应广大用户需求，背钻位置现在完全支持DRC间距规则。（见升级到Allegro17.2-2016的10大理由之4：行业领先的背钻能力）。同时更新的还有标准钻孔间距DRC的行为变化。追溯到16.2版本，我们提供了钻孔DRC来支持 “内层无盘工艺” 功能。该检查功能只有在焊盘被删除、或者焊盘尺寸比钻孔小时（测位焊盘）才有效。从那以...
- 26 Oct 2018
Breakfast Bytes: ERI: CHIPS and Chiplets

Paul McLellan

One of the DARPA programs that is part of the Electronic Resurgence Initiative (ERI) is called CHIPS. This stands for Common Heterogeneous Integration and IP Reuse Strategies. In fact, the CHIPS program started before ERI existed, so I'm not enti...
- 26 Oct 2018
Verification: Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based High Performance Computing Servers

XTeam

On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching system design enablement collaboration, the Cadence Verification Suite is ready for use on Arm®-based high-performance computing (HPC) server environments. Now, all of the Cadence verification software tools you know and love—including Xcelium Simulator—can be run on the Hewlett Packard Enterprise (HPE) Apollo 70 system, which uses…
- 25 Oct 2018
Analog/Custom Design: Virtuosity: Updated ADE Assembler and ADE Explorer Rapid Adoption Kit

Arja H

The Virtuoso ADE Assembler and Virtuoso ADE Explorer Rapid Adoption Kit (RAK) has been updated for IC6.1.8/ICADVM18.1 to cover the new features. These include Setup Library Assistant Worst Case Corners in Run Plan Minor usability improvements
- 25 Oct 2018
The India Circuit: An Ocean Of Opportunity

Madhavi Rao

We were lucky to have Cadence CEO Lip-Bu Tan visit India recently, when he keynoted at CDNLive India. Lip-Bu always has interesting insights. He has always been very positive about the future of the semiconductor industry, and this year was no differ...
- 25 Oct 2018
Breakfast Bytes: Formal Post-Silicon Debug

Paul McLellan

Two outstanding presentations at the recent Jasper User Group were on using JasperGold (JG) for post-silicon debug. The two presentations were from Laurent Arditi of Arm, In Case of Emergency Call 1-800-FORMAL and from Jim Kasak of HP Enter...
- 25 Oct 2018

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.