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Breakfast Bytes: Cadence Cloud

Paul McLellan

Today Cadence announced Cadence Cloud. This is the beginning of a major change in how EDA capabilities are delivered. I doubt that all EDA will move into the cloud—there will certainly be some customers who want to keep some of their computatio...
- 25 Jun 2018
Breakfast Bytes: Remember Virtual CAD? DesignSphere Access? What an ASP Was?

Paul McLellan

Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology services and, in particular, something we called Virtual CAD. The idea of Virtual CAD was to allow companies to outsource their CAD group to Cadence. In effect, we...
- 22 Jun 2018
Verification: Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

XTeam

Welcome back to our series on cloud verification solutions. This is part two of a three-part blog—you can read part one here.

The high-performance computing (HPC) market continues to grow. Analysts say that the HPC market will reach almost $11 billion by 2020—that’s an annual growth rate of almost 20%. Cloud providers and other related companies are putting more and more resources into building solutions for this…
- 21 Jun 2018
Verification: App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog Data Structures

XTeam

Welcome back to the third installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines for SystemVerilog. This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just…
- 21 Jun 2018
Breakfast Bytes: Automobil Elektronik Kongress 2018

Paul McLellan

Once a year for 22 years the electronic divisions of the European automotive industry converge on the small town of Ludwigsburg just outside Stuttgart. Stuttgart is a big enough city, you've probably heard of it. In the automotive world, it is home t...
- 21 Jun 2018
Breakfast Bytes: What's For Breakfast? Video Preview June 25th to 29th 2018

Paul McLellan

https://youtu.be/-fwwmFE6yUs Coming from Automotiv Elektronik Kongress (camera Robert Schweiger) Monday: Embargoed Tuesday: DAC day 1 Wednesday: DAC day 2 Thursday: DAC day 3 Friday: Embargoed www.breakfastbytes.co...
- 20 Jun 2018
Breakfast Bytes: Movie Theater Sound in Your Phone

Paul McLellan

Dolby Atmos is immersive sound. As Dolby puts it: Dolby transports you into the story with moving audio that flows all around you with breathtaking realism Well, there is some level of colorful marketing there, but it really does have to be heard t...
- 20 Jun 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Introduction to ADAS with a Real-Life Example

References4U

In this week’s Whiteboard Wednesdays video, Marc Greenberg, walks us through a typical ADAS system architecture and then provides a real-life testimonial on the value of these systems.

https://youtu.be/EQL4jeD25_g
- 19 Jun 2018
Breakfast Bytes: RSA Wrapup: Song, Darling, Thrun

Paul McLellan

The closing session of the RSA conference was a sort of chat-show hosted by Hugh Thompson, who is the RSA Program Chair. He brought up three people, two of who have featured in Breakfast Bytes posts before. The proceedings started with a session wher...
- 19 Jun 2018
Analog/Custom Design: Virtuoso Video Diary: What's this Net Connected to?

sarahfino

Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where you can identify connections that exist for a net, filter on these connections and save the probe path information to a CSV file.
- 19 Jun 2018
Breakfast Bytes: Why Millennial Engineers Should Work for Cadence

Paul McLellan

Many years ago, when Nokia was at the top of its game—one in every three phones shipped was a Nokia—I chatted to the sister of a friend of mine who was something senior in Nokia finance. I think she was the controller for a good part of t...
- 18 Jun 2018
Academic Network: Academic Track at CDNLive EMEA 2018

Anton Klotz

From 7-9.05 the CDNLive circus made it stop in Munich / Germany for full three days. For Academic Network in EMEA this is the most important event through the year, as we are organizing the Academic Track and invite our academic partners to attend, p...
- 17 Jun 2018
Verification: Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

XTeam

Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud.

For a while now, there’s been a growing interest in cloud-based EDA solutions, but the time wasn’t ripe for production deployment. People had concerns about security and the sustainability of the data centers. But nowadays, public clouds are highly secure, typically more secure…
- 15 Jun 2018
Breakfast Bytes: The Design Infrastructure Alley

Paul McLellan

One of the new things at DAC this year is the Design Infrastructure Alley. The Alley is an initiative from the ESD Alliance and the Association for High-Performance Computing Professionals to highlight the information technology infrastructure,...
- 15 Jun 2018
Breakfast Bytes: Pie and Chips at DAC: ChipEstimate.com and the First Annual Pi Contest

Paul McLellan

In Scotland, there is a traditional dish of pie and chips. But the pie is not a sweet fruit pie, like something Marie Callendar would make, but it is full of minced lamb. And chips are what Americans call fries (except in the phrase "fish & ...
- 14 Jun 2018
System, PCB, & Package Design : What Is COM /JCOM Channel Compliance All About?

Sigrity

In today’s world of double-digit gigabit-per-second data rates it is imperative that engineers properly design and characterize their system to meet standards compliance. This sounds simple enough but actually simulating a high-speed ser...
- 13 Jun 2018
Breakfast Bytes: "I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car"

Paul McLellan

Agatha Christie, looking back on her early life, remarked that she: I couldn’t imagine being too poor to afford servants, nor so rich as to be able to afford a car. Like most of us, I've been the other way around. I've owned a car sin...
- 13 Jun 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - What Really Matters When Selecting IP

References4U

In this week’s Whiteboard Wednesday, Tom Hackett says that PPA is only the tip of the iceberg of requirements to consider when selecting IP for your next chip design.

https://youtu.be/2S6V5RpXECM
- 12 Jun 2018
Digital Design: High-Level Synthesis: The Secret Is Out

dpursley

Gone is the day when companies (our customers) kept their use of high-level synthesis (HLS) quiet, a secret advantage over their competitors. As HLS usage became more widespread, the secret is out, and now the HLS community is talking and sharing experiences with each other.

Take CDNLive, for instance. This year, HLS discussions are happening at the CDNLive shows worldwide. Since it’s extremely unlikely any of you have…
- 12 Jun 2018
Breakfast Bytes: Imec on EUV. Are We There Yet?

Paul McLellan

I already gave an introduction to my first visit to imec in my life in my post If It's Tuesday This Must Be Belgium. My First Visit to imec One of the things I mentioned there is that they have an EUV stepper in their fab, and they work clos...
- 12 Jun 2018
Breakfast Bytes: What's For Breakfast? Video Preview June 18th to 22nd 2018

Paul McLellan

https://youtu.be/puYFl7m50tM Coming from Dilijian Armenia (camera Gary Bengier) Monday: Why Millennial Engineers Should Work for Cadence Tuesday: Wrapup from the RSA Security Conference Wednesday: Dolby DAP Light Thursday: Automotiv Elektronik ...
- 12 Jun 2018
Verification: DMS 2.0 - What's Cool and What's New

XTeam

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and wonderful features to help you use Xcelium to verify your mixed-signal designs.

The level of interaction between analog structures and digital logic is a lot more complex than it used to be. Divide-and-conquer verification isn…
- 11 Jun 2018
Breakfast Bytes: FD-SOI vs FinFET: Dan Hutcheson Re-Runs His Survey

Paul McLellan

Recently, the SOI Consortium held its annual Silicon Valley Symposium. I was only able to attend in the afternoon since I spend the morning at the ESD Alliance workshop on digital marketing (for more on that, see my post Digital Marketing—With ...
- 11 Jun 2018
Analog/Custom Design: Virtuosity: Let's Have Fun with ADE Debugging – Part 1

Kabir

Over the years, we have seen our customers’ usage of ICRPs increase dramatically. It is now quite common to run 1000s of simulation points using 100s of ICRPs. And as this usage has increased, one of the challenges that has emerged is how to debug issues with ICRPs and job distribution, which is the topic of my write-up. So, what is it that I’m trying to address? Does the following sound familiar? User hits green button…
- 11 Jun 2018
Breakfast Bytes: Why Did EDA Have a Hardware Business Model?

Paul McLellan

Business models are really important. Just ask any internet startup company that has lots of users and is trying to work out how to monetize them. It is a lot easier to get people to use something for free, much harder to get people to pay for s...
- 8 Jun 2018

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