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As my colleagues Adam Sherer and Joe Hupcey reported last week, Cadence has just published "A Practical Guide to Adopting the Universal Verification Methodology (UVM).” It is the world’s first book on the UVM. Or is it? The definition of "book" has become rather fuzzy these days. Could the UVM Reference Manual and User Guide published in PDF form by Accellera qualify as books? Would we still say that we had "published…

There are several ways that Incisive Formal Verifier (IFV) can be set to evaluate properties in parallel. The bottom line is that customers using these “productivity flows” have been dramatically increasing their verification throughput – turning days into hours, and hours into minutes.  In one customer case, what had been a 6 day run came in under 4 hours using this capability – a throughput improvement…

The Allegro Global Route Environment (GRE) has expanded its capabilities in the area of bundled editing in the SPB16.3 release.

It’s now easier to copy, move, and split bundles.

Copy Flow lets you copy the flow path from one bundle to another. Its primary goal is to allow faster creation of the designer’s flow plan. If you have repeated circuits or regions of your design that have a large number of bundles that will…

I know, it's been a long time since my last post.  You see, we've finally arrived at a topic near and dear to my heart -- ADE XL.  The reason for my hesitation in approaching this topic is not that it's difficult, but rather that there's so much to talk about that it's hard to know where to start.  It's a bit like trying to write a guidebook for the Louvre.  The place is enormous.  Do you describe the…

A while back we were talking about how to programatically troubleshoot timing violations in Encounter.  That post recieved a lot of good comments (thanks!) but one in particular touched on a point that I've worked on with other users, so I thought to raise it up for visibility here and go more in depth on the topic.  Nataraja G asks:

"how can we get the delay values associated with that cell ? is it possible!"…

Earlier today a new book called "A Practical Guide to Adopting the Universal Verification Methodology (UVM)" was released.  As a complement to this detailed post on the book, I've interviewed its authors, Sharon Rosenberg and Kathleen Meade.  In this video, find out from the Sharon and Kathleen how they've worked to build upon the wealth of reference material already available for UVM (like the open source…

A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the first book published on the emerging Accellera UVM. Written by the main authors of the user guide in the UVM release, this book provides more details and extends the methodology to address system level challenges. Unlike some books about earlier methodologies, it never assumes verification engineers are sheep that can only follow simple…

Mark your calendar and sign up for the two upcoming free verification sessions sponsored by Cadence. Space is limited. So, please sign up today!

JULY 21^st

All-Day, Hands-on technical workshop in Irvine, CA

Topic: Advanced Verification Techniques using e/SV Workshop

Learn how to architect an advanced testbench using OVM/UVM that contains generation, coverage and checking and much, much more.....

This workshop will focus on…

There has been a lot of on-line discussion since DAC about whether the Universal Verification Methodology (UVM) is ready for prime time. My last three blog posts (1 - 2 - 3) addressed some of the reasons why I strongly believe that the UVM is ready and why you should consider it for your next verification project.

In the middle of my series, Mark Glasser from Mentor posted in his blog that "Eventually there will be a tipping…