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SoC and IP: Last call for Denali’s DAC party: Anaheim, June 14

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It’s the Denali DAC party for 2010. The big one. With the bells and whistles. With the EDA360 Idol contest. The one with the outrageous and copious quantities of music, fun, and booze. At the House of Blues. That one.

There’s no registration at DAC. You must register this week at http://a.denali.com/4H. Then go to Denali’s booth first thing Monday morning at DAC to pick up your ticket. You see, the party’s Monday night…
- 7 Jun 2010
Verification: Bloggers and Journalists and Gadflies, Oh My!

tomacadence

There has been quite a bit of discussion out in the blogosphere about the similarities and differences among traditional journalists, paid bloggers, "independent" bloggers, industry gadflies, and commentators of all sorts in EDA (and electronics in general). See threads from John Blyler and Harry Gries on this topic, including how DAC is evolving to handles the different types of attendees, whether the Deep…
- 7 Jun 2010
SoC and IP: An inconvenient truth about using DDR3 SDRAM for embedded designs

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DDR (double data rate) memory chips mounted on DIMMs have long been the mainstay of the PC and server industries. The resulting sales volumes often make these DIMMs the best value available today in terms of cost per bit. PC DIMMs have been 64 bits wide through all DDR generations from the original DDR (also called DDR1) parts to today’s DDR3 chips. Many embedded designs also use PC DIMMs because their high sales volumes…
- 4 Jun 2010
Verification: EDA360 And The "Paperback Computer"

jvh3

Have you ever heard an assertion that's so intriguing and farsighted that it sticks in your mind over a period of years; even decades? Imagine that the given thought is so resonant, that whenever a related innovation appears the idea is instantly recalled as if you were just talking about it. For me, one such notion is the "paperback computer" -- a computing device so cheap that it's as physically inconsequential…
- 3 Jun 2010
SoC and IP: Storage Analyst Jim Handy says “NAND Cache is Back!”

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Storage analyst and Grand Poobah Jim Handy has just released a free White Paper titled “NAND Cache is Back: SSD Performance at an HDD Price” and it’s worth a look if you are interested in either the market for NAND Flash or have any interest in PC and server storage. The reason this White Paper is worth a look is because Handy goes into substantial quantitative detail with extensive graphs in his analysis and mapping…
- 3 Jun 2010
SoC and IP: Kingston shows HyperX USB 3.0 SSD prototype at Computex

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Earlier, this blog reported on OCZ’s Enyo USB 3.0 SSD and now at a private event held at this week’s Computex show in Taiwan, memory vendor Kingston has shown a prototype USB 3.0 SSD (as reported by Tom’s Hardware and Softpedia). Slated for August availability, the HyperX SSD will reportedly be offered in capacities of 64, 128, and 256 Gbytes. The USB 3.0 connection gives the drive peak read and write speeds of 195 and…
- 3 Jun 2010
Verification: Making an EDA360 System Realization Investment Through Standards Support

Steve Brown

Cadence is a sponsor of the Open SystemC Initiative (OSCI) standards organization. We are providing finanical and leadership resources to facilitate the creation and promotion of standards for system development. We continue to invest in OSCI and its...
- 3 Jun 2010
SoC and IP: Introduced at Computex: OCZ’s speedy RevoDrive brings PCIe SSD to consumer-class PCs

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PC add-on vendor OCZ plays in several high-performance PC component markets including DRAMs and SSDs. The company is at the Computex 2010 event in Taiwan this week and is reportedly introducing a high-performance SSD on a PCIe x4 plug-in card. Anandtech’s coverage of the introduction reports that the RevoDrive is based on a pair of Sandforce SF-1200 controller chips in a RAID configuration. (The photo on the Anandtech…
- 2 Jun 2010
Verification: C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

Steve Brown

In the continuing effort to make high-level synthesis more viable to mainstream RTL designers, Cadence has released version 10.1 of the Cadence C-to-Silicon Compiler (CtoS).This new release continues the recent trend towards overall ease-of-use and Q...
- 2 Jun 2010
SoC and IP: Hitachi’s Z HDDs: Will 2.5mm less height make a difference? For SSDs?

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Hitachi just shaved 2.5mm off of the top of its 2.5-inch laptop hard drives, producing a line of 5400- and 7200-rpm, single-platter HDDs called the Z series (Z is the height axis, get it?) with capacities of 160 to 320 Gbytes. (Press release here.) Although there are standard specs for a 2.5-inch drive’s width and depth, height is not part of the size spec but some heights have become de facto standards. Initially, 2…
- 1 Jun 2010
SoC and IP: More details on and system-design implications of the Hitachi-LG Data Storage HyDrive Optical/Solid-State Disk

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As discussed last week in this blog, Hitachi-LG Data Storage (HLDS)--an OEM vendor of optical drives that’s a joint venture between Hitachi and LG--introduced a combo optical/solid-state drive called HyDrive last week at Computex 2010 in Taipei with a few more technical details about the drive. (See: How does a hybrid SSD/optical drive make sense?) The initial version of the HyDrive will reportedly be based on a DVD burner…
- 1 Jun 2010
System, PCB, & Package Design : What's Good About AMS Simulator And Cursors? You’ll Need The SPB16.3 Release To See!

Jerry GenPart
With the SPB16.3 release of AMS Simulator, several new cursor enhancements are available:
Setting cursor width and color
Placing cursors across multiple traces and plots
Exporting and copying cursor data
Dockable cursor window

Read below to see these new features.
_______________________________________________________________________________________________________
Setting cursor width and color

The Cursor Settings tab of the…
- 1 Jun 2010
SoC and IP: ST Microelectronics’ SPEAr1300 embedded MCU features 600MHz dual-core ARM Cortex-A9, DDR2/DDR3 SDRAM controller

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A few days ago, this blog discussed the “big resistor” model of SDRAM power consumption (see Marc Greenberg’s “big resistor” model of semiconductor DRAM power consumption) and that blog entry ended with this statement:

“It might also be a very good idea to design your system so that it can accommodate more than one DDR variant. That way, time and circumstance can determine which DRAM technology gets used at any given…
- 28 May 2010
Verification: TLM 2.0 As Part Of The EDA360 Vision

Ran Avinun

Ann Steffora Mutschler recently covered in her blog the progress the industry has made with OSCI transaction-level modeling (TLM 2.0) and the requirements moving forward. Per my quote in the blog, Cadence is a big advocate of standards-base...
- 28 May 2010
System, PCB, & Package Design : Catch A Full-Wave Summer Kickoff Webinar: CST 3D Extraction Integrated With Cadence SiP

TeamAllegro

Is there anyone who does not carry a mobile communication device anymore? Sending and receiving phone calls seem to be just a minor feature on these devices nowadays. With texting, email, Wi-Fi, GPS, camera, video, image recognition softw...
- 28 May 2010
SoC and IP: How does a hybrid SSD/optical drive make sense?

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Some combinations like chocolate with peanut butter, ice cream with peanuts and chocolate sauce, and HDDs with NAND Flash caching make obvious sense. Other combinations don’t make such an obvious match. In these cases, people need extra convincing. LG and Hitachi are suggesting just such a non-obvious combo as a concept: an optical drive and NAND Flash. Optical drives? Aren’t they on the way out, like floppy disks? Not…
- 28 May 2010
Verification: EDA360 Is More Than Design IP Plus Software Drivers

tomacadence

I checked my Linked-In messages the other day and saw a survey by Girish Patil with the provocative question "Is EDA360 the same experiment that Phoenix Technology tried a decade ago with the acquisition of Virtual Chips and Sand Micro?" Well, that was an interesting link between my past professional life and my role at Cadence today.
Phoenix Technologies was -- and remains -- a leading provider of BIOS for…
- 27 May 2010
SoC and IP: Does Samsung really scare Japan? EETimes’ Junko Yoshida thinks so.

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EETimes' Junko Yoshida just published an article titled “5 reasons why Samsung scares Japan” (http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=225200248) that discusses five major reasons why Samsung has become the manufacturing powerhouse that it is today. There’s no question that in semiconductor memory, Samsung is a true industry leader. According to DRAMeXchange, Samsung was the dominant player in semiconductor…
- 27 May 2010
SoC and IP: Marc Greenberg’s “big resistor” model of semiconductor DRAM power consumption

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Too many DRAM choices. If you want low power DRAM, do you choose LPDDR1, LPDDR2, DDR2L, DDR3L, or what? It’s not an easy choice because of all the variables involved: the peak and average transfer rates, the power supply voltages, and the IC manufacturing process technology used--just to name three. In addition there are the DRAMs’ various operating modes and the corresponding current consumption in each mode. The modes…
- 25 May 2010
SoC and IP: OCZ Enyo USB 3.0 SSD reviewed by PC Perspective video

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Earlier, we covered the announcement of OCZ’s Enyo USB 3.0 external SSD. Now PC Perspective has created a pretty interesting video review of the drive. OK, the review starts kind of slow and seems to have very little technical meat but you might want to let the video play until they disassemble the drive to reveal the product’s interesting silicon guts. That’s when you’ll learn all you need to know about the chips inside…
- 25 May 2010
SoC and IP: InfoWeek video series chronicles storage and SSD Evolution. Part 1 runs 8 minutes, 42 seconds

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Can you spare nine minutes to get a really good grounding in SSD concepts? No? How about eight minutes and forty-two seconds? Ah, now we’re talking. Information Week and with Storage Switzerland’s Lead Analyst George Crump have produced an excellent 4-part video tutorial series on SSDs. Each part runs less than 10 minutes and Part 1 covers the technical side of storage evolution in a concise and interesting way that’s…
- 25 May 2010
System, PCB, & Package Design : What's Good About Browsing For Power Pins in Capture? It's In SPB16.3!

Jerry GenPart

The SPB16.3 release of Allegro Design Entry CIS (Capture) now allows you to browse power pins in your design. In Capture, most of the design’s power pins are invisible, which makes it difficult to find power pins. The new "browse power pins" capability will help you find the pins faster and increase your productivity.
In Capture, power and ground supply pins are referred to generically as "power pins."…
- 25 May 2010
SoC and IP: Squeeze bandwidth inefficiencies out of DDR DRAMs in memory subsystem designs

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This blog starts with a simple, sad truth: DDR DRAMs are naturally inefficient. If this statement bothers you, just get over it. All human-made artifacts have inefficiencies and DRAMs are no different. However, there are things you can do to squeeze every bit of bandwidth efficiency out of a DDR DRAM and your efforts can be rewarded with significant performance gains. You can improve memory-subsystem bandwidth by 20-30…
- 24 May 2010
Digital Design: Mixed Signal: Why The Sudden Attention?

PeteMc

With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors will use “mixed signal” somewhere in their company’s messaging. Last year it seemed that nearly everyone wanted to jump on the mixed signal “bandwagon” … so what caused this sudden jump in interest in mixed signal?

We all know that mixed signal design is not new. It’s been around for about 20 years (give or take), but there has…
- 24 May 2010
SoC and IP: Why is it so difficult to interface with DRAMs?

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One of the maxims in the world of system design is that it has always been relatively hard to interface with DRAMs and make them work properly in all possible operational situations. This isn’t a new situation. It’s been hard to interface with DRAMs since the day they were first introduced back in October, 1970 when Intel rolled out the first commercial DRAM, the 1-kbit 1103. Intel’s 1103 DRAM was a PMOS chip that introduced…
- 24 May 2010

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