Community

In my last post I shared how my annual tour of the tour of the ESC show floor inspired me to ask the community their preferences on trade show formats.  Since I'm not certain how persistent these free survey sites are, allow me to replicate a snapshot of the survey results from the official results page below:

Question: Which type of event do you prefer in general?
Booth-centric events (like ESC or DAC) --  44%, 8 res…

In my previous blog on noise analysis accuracy, I mentioned something called “double-clocking” and a few of you since then have asked for more information on what it is... So as a follow-up to that bog, I’ve invited our resident noise analysis expert Trisha Kristof, who’s been working on our SI analysis since the CadMOS CeltIC days, to guest blog on this topic.

A note from Trisha Kristof on…

IC designers and foundries typically have different objectives. IC designers want to achieve the greatest performance while performing the least amount of guard-banding. Schedules and predictability are also paramount concerns for designers. IC Foundries want designs to adhere to design for manufacturing (DFM) and design for yield (DFY) rules and recommendations for their advanced process nodes to achieve the highest…

The constraint solver is a powerful and fun to use tool.  Actually, it is so much fun that  sometimes people tend to use it in cases where generation is not required.  Of course, like any other algorithmic engine, the “price” of using the constraint solver is paid in performance – both memory and CPU.  This price is acceptable whenever the solver is used to process complicated generation problems, but it…

This is the last in the series of Constraint Construction blogs! Today we're going to go over DESIGN RULES and MODES OF OPERATION.

DESIGN RULES: Follow them, or else...

Often times, these rules are indeed set in the timing library. But perhaps you want sharper transitions in your design to reduce noise issues. Or maybe you want to give yourself some margin of safety with minimum capacitance. Let's go over the…

That's right - the SPB16.2 release now includes support for Physical and Spacing (P&S) Constraints from within the Design Entry HDL Constraint Manager.

Prior to this release, you could only set electrical constraints in Design Entry HDL Constraint Manager (CM). Beginning with the SPB16.2 release, in addition to electrical constraints, you can use Constraint Manager connected to Design Entry HDL to create, view…

I'll be live blogging from the Cadence Campus in San Jose today.  We're doing a seminar that focuses on the 8.1 release of the Encounter Digital Implementation System, and we'll be focusing on the following areas:

• Design Closure
• Mixed Signal
• Low Power
• Advanced Node
• Analysis & Signoff

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware e coding to point out a new blog we just discovered on "e verification" by Shivayogi, "a Senior Design Engineer, working in the field of verification for more than 5+ yrs".

http://e-verification.blogspot.com/


Team Specman, and we dare say Specmaniacs everywhere, welcome this new resource to the community!

Here are…

Last Wednesday I walked the floor of the Embedded Systems Conference (ESC), with the added bonus of catching the panel discussion on "Who's Taking Over Whom - Is EDA moving Into Embedded or Embedded into EDA" supported by Mac (a/k/a Michael McNamara). While this panel was very engaging, (check out fellow blogger Steve Brown's account here), instead of blogging about the panel I've been inspired to step…

Building on Part 1 where I talked about the “do’s and don’ts” of List performance, in this segment on performance-aware coding I’ll show you some memory saving tips.  We base this segment on base types (geeky pun intended) …

Base types extensions
Creating base classes with functionality that is common to many environments is a good practice.  In this way you “develop once” (and even more…

Well, are you still wondering what Virtuoso has to do with the SATs and The Dark Knight?  Well, thanks for indulging me, I hope the suspense wasn’t too much to bear! As I mentioned in part 1, if you had taken the January 2009 SAT test, again, like my daughter did, you had this as one of your essay prompts:

Prompt 1
Think carefully about the issue presented in the following excerpt and the assignment below:…

In the late 70's and early 80's system level PCB and Digital IC physical design evolved from manual Rubylith and Digitizing methods. If I haven't dated myself already with the terms Rubylith and Digitizing I know that I'll really be dating myself with my history at IBM.  While working for IBM in the General Products Division San Jose, CA during this period of time I used an IBM proprietary EDA application…

This past week, there has been a very interesting discussion on the "icu-pcb-forum" Email alias. Most of the people have migrated to our Cadence Support forums, but there are still a few that use the "icu-pcb-forum" Email alias.

The topic - Schematic drafting practices.

There are some "veteran" designers (several with more than 25 years of experience) posting their perspective and company practices…

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5 part series on performance-aware e coding guidelines.]

As all Specmaniacs know, the "e" language is flexible and powerful, containing many constructs that allow users to implement virtually anything. The downside of this freedom is that sometimes developers do not make the best choices when it comes to writing efficient code…

Let me be among the first in the Cadence "blogger corps" to welcome Richard Goering to the team. Anyone who has been involved in EDA in the past 20 years surely knows and respects Richard.

Personally, I spent about 10 of those years in Design, Verification, and CAD management, where I always read Richard's articles and columns for their keen insight into the tools I used or should consider using. The last 10…

At a purely technical level, Process Design Kits are fairly innocuous. They are used to enable custom IC design flows. A Process Design Kit (PDK) includes device models, schematic symbols, netlisting procedures and parameterizable cell layout generators. Physical verification rule decks and a parasitic extraction technology file are usually included in the kit. Quite a few of the tools used in custom IC, such as placers…

Every analog circuit design goes through some kind of electrical validation step before release to manufacture. The depth and breadth of this testing depend on the design itself, the end application and of course that all important deadline. When it comes to custom design, there is also an individual factor, as different engineers have different ideas on what validation is required. For example, on one end of the spectrum…