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Documentation.  This single word tends to sends shivers up the spine of many an engineer.  People like to code.  It's fun.  It's exciting.  You can simulate your code, view waveforms, debug it, collect coverage on it and play with it.  Let's face it, a Word document simply pales in comparison. 

Now, I am not saying that anyone should start coding up your verification environment without an up front plan in place…

Imagine the complex scenario whereby you start the *same* sequence on multiple sub-drivers.  Naturally each started sequence has its own execution thread, so how do you refer to all the started sequences, and/or know when they have finished? 

Consider the following steps, followed by a code example that references the AXI UVC.

Step 1 - Add "has_started" and "has_ended" flags to "any_sequence", check why aren’t they there…

The OVM user reports from Xilinx, SiRF, and ST at the DVCon luncheon were real engineer-to-engineer presentations, not the shiny presentations this marketing guy is accustomed to giving.  While my partners in blogging have reported on the OVM in a Multi-language World tutorial and luncheon, I wanted to follow-up with a few more details.

Tutorial

We just received the numbers from DVCon and it looks…

[Preface / Disclaimer: I haven't yet had the pleasure of working closely with Cadence's own Hosted Design Solutions team, so the following will likely reveal ignorance of strategies and solutions that they already have in place to address the issues outlined below.  However, given the ideas this panel has inspired, you can be sure I'll be closing this personal information gap in the very near future ...]

A surprise…

(Note: Click here to view Bill Acito's webinar.)

If you caught Jerry GenPart's blog in November on Advanced Plating Bar Checks and wondered what else is new in APD 16.2, you are in luck.  On Wed, March 18, Bill Acito, Product Engineer, will review the long list of new technology available in the latest release.

As an example, you'll see how the latest HDI technology in the Allegro platform is supported in APD / SiP…

Well ... if you like tweaking and tuning an environment to suit your needs, Allegro Design Entry HDL (DEHDL or previously known as ConceptHDL) has plenty to offer.

I began in the Blog-sphere-posting-world of Cadence with one of my first posts titled - "How many DEHDL (Concept) designers customize their DEHDL environment?" You can read the details here

Although I asked about this almost a year ago, the relevance…

Have you ever tried manually moving IO cells in your design and thought: "This would be a lot easier if these IO cells could snap to a row, just like standard cells do"? Well, now they can! One of the new features in Encounter 8.1 is the support of IO rows.

First, you will have to enable the IO Row Flow (it is not on by default). After importing your design, type:

    setIoFlowFlag 1

This setting will be preserved…

In my last post I discussed how to use save / restore in the Cadence Incisive Simulator to create checkpoints for designs that contain SystemC. The algorithm for SystemC save / restore is fundamentally different than the algorithm for HDL designs. Although most of the functionality is equivalent between the two styles, there are a few differences.

During restart, all internal variables are restored to their saved values…

I am very excited about an event that Cadence low-power R&D and technical experts are hosting in Europe and eventually in other regions. The nice part about this is that it allows for informal discussions between engineers. I recently sat down with one of the presenters to find out what these events are all about.  

If the embedded video fails to launch please click here.

Bring your low power design issues…

In order to bring our technology and developers closer to you the MMSIM team is currently offering a seminar/workshop Series.  The morning session consists of a technology overview, R&D presentation, and talk on the nuts and bolts of the simulation technology which is then followed by a hands on workshop in the afternoon.

Workshops/seminars: http://www.cadence.com/workshops

Schedule: http://www.secure-register…

Part 3. EXCEPTION PATHS: For Every Rule, There Is An Exception

More often than not, I'll start an optimization on a block only to have it result in thousands of timing violations.  Many times, the culprit is a missing path exception constraint.   When you see timing violations that are suspicious, ask the RTL/constraint developer whether there are exceptions to the timing rules you're trying to meet. Let's go over some…

Specman 8.2s2 adds new Application Programming Interface (API) methods to sequence drivers, enabling enhanced flexibility to users working with layered protocols, users looking for performance enhancements, and more. Although this feature is still considered Early Adopter (EA), I suspect some of you sequence experts will be quite excited to begin using this feature ASAP.

Introduced years ago in eRM (now OVM-e), sequences…

[Team Specman welcomes back the Technical Publications Team to guest blog]

A logical follow-on to a prior tip on searching for single character words is this quick tip on how to search for special characters.  Specifically, the Search function in Cadence Help will not automatically succeed on search terms that contain any of these special characters:

+, -, &&, ||, !, (, ), {, }, [, ], ^, ", *, ?, :, and \.

To…

An ecosystem as defined by Webster's is a "system formed by the interaction of a community of organisms with their environment". This describes perfectly the methodologies so common for analog and custom IC design.  Unable to strictly rely on automation or synthesis, the custom design flow is chock full of interactive niche methodologies that have become the differentiator of most analog IC suppliers…

Coplaner waveguides (CPW) are widely used in packaging, high speed designs and on silicon. These structures are now supported in Allegro PCB SI.

The figure below shows a typical coplaner waveguide. The important distinction for a segment to be a coplaner waveguide is a segment "W" surrounded by two large shapes. In order to detect coplaner waveguide segments while traversing a net, there needs to be a Shape window. The…

Welcome to part 5 of the Exploring the Virtual Platform series. This is probably (hopefully) the last post in the series related to the embedded software aspects of the Virtual Platform before I move to the hardware aspects of the platform and topics that are probably more familiar for Cadence users.

This post covers BusyBox - The Swiss Army Knife of Embedded Linux. Part 4 covered some details of how to cross compile…

Panels are some of the most popular sessions at many technical conferences. Getting a half-dozen opinionated, outspoken engineers to argue over a topic of interest to the conference attendees is clearly a good idea, and quite often it works as intended. I used to attend the International Test Conference (ITC), where the evening panels (with bottles of wine visibly being consumed by the panelists) drew audiences in the…

At risk of being lost in all the excitement of DVCon 2009 last week, my colleagues on the VIP Team announced a truly unique experiment, where the whole MIPI Verification IP product is available to try out now in the Xuropa Online Lab.  The important thing to note is that this is not some cheesy Flash demo, or a video of an AE giving a demonstration.  The Xuropa Online Lab is hosting the real product for you to run and interact…

Joe Hupcey has done his usual fine job of documenting DVCon (day 1, day 2, day 3) but I want to take a step back and summarize what has surely been one of the busiest weeks ever for the Cadence functional verification team. 

Our DVCon activities included a booth in the Expo, an OVM tutorial, an OVM lunch with three customer presentations, a panel on mixing simulation and formal, and several technical papers. 

Also, we participated…

Originally architected for multiple languages, the OVM is now available for all three standard languages used most commonly in verification SystemVerilog, e, and SystemC.  The e and SystemC libraries comply with the OVM 2.0.1 methodology and are available as open-source on OVM World.

All Languages in One Methodology - How?

The key to this all-for-one methodology is an architecture built from the ground…

Today I was able to cover a paper on "OVM-based Methodology for Low Power Designs", and the panel titled "Mixing Formal Analysis with Simulation: Why, When, Where, and How?"  Click here for some annotated photos.

Notes:
* Given there is much to say about the topic of Low Power in general, and OVM in specific, I felt authors John Decker and Neyaz Khan did a great job in compressing such an expansive subject…

ESL Virtual Platforms (systems or sub-systems) require heterogeneous libraries of TLM IP models that can interconnect. Indeed, the OSCI TLM2 interfaces appear to be the only viable solution to solve this interoperability issue. Moreover the IP you need is not always available (because it is a new IP or a custom IP or because it is not yet available from your 3^rd party provider). For whatever reason, you have…

Checkpoint Restart for Digital and Mixed Circuits will allow PSpice users to set checkpoints while doing a transient analysis for digital and mixed circuits, saving all the transient information onto the disk and then allowing users to restart the analysis from any of the saved checkpoints.

The CheckPoint Restart feature lets you save the state of a transient simulation at different moments as Checkpoints. One can specify…

Here are some pictures from DVCon 2009 Day 2, focusing on the OVM Case Studies lunch, some panel discussions, and a few more snapshots from the show floor click here.

Notes:
* The OVM Case studies luncheon showed a surprising variety of use models and applications, with multi-language interoperability under the OVM umbrella being a key factor in each of the very different projects outlined.  (Be advised that the photos of…

As an Applications Engineer, the first demonstrations you deliver of a new technology are always the most interesting.  The questions you receieve are all over the map and your skills in thinking on your feet are put to the test.  Personally, I really enjoy this learning phase and as I was putting together this screencast, I was reminded of the first demo I ever gave of First Encounter back in 2001.  The primary question…