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Verification: Temporals, Reset, and Test Phases

teamspecman

One of the biggest challenges in dynamic functional verification is testing Reset – resetting the DUT during simulation and check DUT operation afterwards. The main challenges are propagating the reset information in the testbench, and adjusting the components behavior.

For performance and accuracy, it is best to have one agent controlling and monitoring the reset, rather than each and every agent monitoring the…
- 11 Mar 2018
System, PCB, & Package Design : Thermal Analysis of Package/PCB Systems: Challenges and Solutions

Sigrity

More and more package/PCB system designs are requiring thermal analysis. Power dissipation is a critical issue in package/PCB systems design which requires careful consideration of the thermal and electrical domains. To better understand therma...
- 9 Mar 2018
Breakfast Bytes: Spanish Flu Is 100 Years Old on Sunday

Paul McLellan

This Sunday, March 11, is the 100th anniversary of the outbreak of Spanish flu in 1918, when patient zero was diagnosed. Anniversary usually implies something good, but Spanish flu was anything but. Albert Gitchell, an Army cook at Fort Riley, K...
- 9 Mar 2018
Analog/Custom Design: Virtuosity: Exploring Histories

Arja H

OK we heard you, you want to be able to specify Virtuoso ADE Explorer history names before simulation and you want these histories to increment just like they do in Virtuoso ADE Assembler, right? Let's look at how to do this.
- 8 Mar 2018
Analog/Custom Design: Virtuosity: Do I Need To Run a Simulation To Plot From a Text File?

Arja H

You'll be glad to hear the answer is No! In Virtuoso Visualization and Analysis, we have a Calculator function available called getAsciiWave, which will create a plot from your text file without the need to create a schematic or a testbench, or run simulation. Let's see how easy it is with the help of an example.
- 8 Mar 2018
Breakfast Bytes: embedded world: Mark Papermaster of AMD

Paul McLellan

The opening keynote from embedded world in Nuremberg was by Mark Papermaster, who is the CTO of AMD. The second-day keynote was by Andrea Martin, who is CTO for that part of IBM. The first thing to point out is that AMD and IBM are not the first comp...
- 8 Mar 2018
Breakfast Bytes: 3nm Cadence and imec

Paul McLellan

I started Breakfast Bytes on October 8, 2015, my first day back at Cadence. The very first (real) post was Cadence and imec Announce World's First 5nm Tapeout. I had to find out what I could about the test-chip, write it up, and publish, a...
- 7 Mar 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Error Correction Code Implementations in Memory Controller Designs

References4U

In this week's Whiteboard Wednesdays video, Jing Liu provides a simple explanation of the in-line and out-of-band methods of Error Correction Code (ECC) implementation in memory subsystem designs.

https://youtu.be/ejYImUgMXTI
- 6 Mar 2018
Verification: App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right For You

XTeam

Welcome to another App Note Spotlight!

One of the biggest issues facing verification engineers is the question of reducing elaboration time. Using incremental elaboration (MSIE) can greatly reduce that time—but that raises a new question: between the two MSIE flows, which one is right for you?

Those two MSIE flows are single-xrun MSIE, and multi-xrun/xmelab MSIE. Single-xrun (1-xrun) MSIE is the simplest; all you…
- 6 Mar 2018
Breakfast Bytes: Spectre with a Red Hat, part 2

Paul McLellan

This is the second post about Red Hat's John Masters presentation at FOSDEM 2018 presentation Exploiting Modern Microarchitectures: Meltdown, Spectre, and Other Attacks. The first part appeared in Breakfast Bytes yesterday. Todays' post covers S...
- 6 Mar 2018
Breakfast Bytes: Spectre with a Red Hat

Paul McLellan

A couple of weekends ago it was FOSDEM 2018, the largest conference on open source in Europe. It was held in Brussels. In keeping with the open source ethos, it was free, anyone could go, there was no registration, and all of the dozen or more parall...
- 5 Mar 2018
The India Circuit: Incubators, Accelerators and Fabless Chip Design at IESA Vision Summit 2018

Madhavi Rao

This week we had one of the Indian semiconductor industry’s biggest and most well-attended conferences, the Indian Electronics and Semiconductor Association (IESA) Vision Summit, in Bangalore. This event is now in its 13th year and attracts the...
- 1 Mar 2018
Breakfast Bytes: Engineers, and How to Manage Them

Paul McLellan

I've covered various aspects of an EDA company: sales, marketing, application engineers, even being the CEO. Today, it is the turn of engineering. My background is engineering. I started my career writing DRC code and the moved on to create VLSI ...
- 1 Mar 2018
Breakfast Bytes: What the FEC is Forward Error Correction?

Paul McLellan

What is forward error correction (FEC)? It is automatically correcting errors in transmitted network data (and sometimes detecting some errors that are too severe to correct). The reason it is important is that communication channels are noisy, ...
- 1 Mar 2018
Breakfast Bytes: What's For Breakfast? Video Preview March 5th to March 9th 2018

Paul McLellan

https://youtu.be/YesJPmKCeio Coming from Embedded World, Nuremberg (camera Robert Schweiger) Monday: Spectre with a Red Hat Tuesday: Spectre with a Red Hat 2 Wednesday: Embedded World Keynotes Thursday: Cadence and ime...
- 1 Mar 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Unpacking the DFI Low-Power Interface

References4U

In this week's Whiteboard Wednesday, John MacLaren describes the operation of the DFI Low Power Interface to reduce PHY power consumption.

www.youtube.com/watch
- 27 Feb 2018
Breakfast Bytes: Embedded World 2018: Dreaming of Electric Cars

Paul McLellan

I am at embedded world in Nuremberg. One thing that is not here is warm weather. All that I can say is that it is warmer in Nuremberg than Munich, -7ºC instead of -11ºC. People don't remember it being this cold for many years (although ...
- 27 Feb 2018
SoC and IP: Why Software-Based GPS Is Great for Location-Based IoT Applications

PaulaJones

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo of a software-based GPS receiver from Galileo Satellite Navigation running off a Cadence Tensilica Fusion F1 DSP. It’s a very impressive demo—come by...
- 27 Feb 2018
Breakfast Bytes: How Many Journalists per Square Acre?

Paul McLellan

It doesn't matter how low your standard is for science journalism, the journalists always seem to manage to go lower. I realize that the sort of people who go to journalism school tend not to be the most scientific. In fact, given the employment ...
- 27 Feb 2018
Analog/Custom Design: Take Advantage of Advancements in Real Number Modeling and Simulation

msteam

Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor…
- 26 Feb 2018
Verification: Xcelium and Cavium: What’s the Deal?

XTeam

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers now. While that’s all well and good, why is it such a big deal? Well, Cadence gathered up Ziv Binyamini, Gopal Hegde, and Ann Keffer to answer just that question in a video:

https://youtu.be/QTN6goFWWBo

What does it mean that Xcelium is now available on Cavium’s Thunder X2 servers? Well, the Thunder X2 brings a lot of advantages…
- 26 Feb 2018
Breakfast Bytes: Patents: Licensed by the Ton

Paul McLellan

I wrote recently about What Happens in a Patent Lawsuit? Today, I want to look at patents from a higher level: why do we have them, and how well do they work in the semiconductor and EDA industries. The Patent Tradeoff The basic “tradeoff&rdquo...
- 26 Feb 2018
SoC and IP: Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

tomhackett

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers are currently in transit around the world? It turns out that no one knows for sure, but the best guess is that there are about 20 million containers in service today. And it's a safe bet that those containers are carrying…
- 23 Feb 2018
Breakfast Bytes: How Do You Get to Be CEO?

Paul McLellan

I wrote last week about Being CEO and I said that I'd done it twice in my career. But I omitted an important point: how do you get to be CEO? I assume we are talking about a small company, or a startup. But, in fact, a private equity firm f...
- 23 Feb 2018
Analog/Custom Design: Virtuosity: New Eye Diagram Measurements

Arja H

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create eye diagrams, add masks and also calculate some standard measurements. The measurements have recently been enhanced by adding more jitter calculations, maximum eye height and width calculations, level annotations and Bit Error Rate (BER) curves.
- 23 Feb 2018

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