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Analog/Custom Design: Virtuosity: New Eye Diagram Measurements

Arja H

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create eye diagrams, add masks and also calculate some standard measurements. The measurements have recently been enhanced by adding more jitter calculations, maximum eye height and width calculations, level annotations and Bit Error Rate (BER) curves.
- 23 Feb 2018
Verification: New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

DimitryP

As discussed in the previous installment of this blog, a new class of atomic transactions was introduced in the AMBA® 5 ACE/AXI specification to make operations at the remote locations more streamlined and efficient. We have considered an example of AtomicStore transaction with ADD operation and discussed why it was more efficient than relying on the older semaphore-like exclusive operations. In this installment of…
- 22 Feb 2018
Breakfast Bytes: What's For Breakfast? Video Preview February 26th to March 2nd 2018

Paul McLellan

https://youtu.be/wq86edcqTdw Coming from Building 10 lobby (camera Sean) Monday: Patents Licensed by the Ton Tuesday: How Many Journalists per Square Acre Wednesday: embedded world Thursday: What the FEC is Forward Error Co...
- 22 Feb 2018
System, PCB, & Package Design : SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)

Sigrity

Backchannel Training Another capability related to equalization adaptation is backchannel training. Many high speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide i...
- 22 Feb 2018
Breakfast Bytes: Paul Kocher: Differential Power Analysis and Spectre

Paul McLellan

Paul Kocher is a legend in security. A couple of weeks ago SiFive hosted a seminar by Paul. They do these regularly, usually on a small scale, but this one required a large conference room in the San Mateo Marriott across from their offices. Ev...
- 22 Feb 2018
Digital Design: Wind of Change in Hardware Design

dpursley

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I stepped out of the office yesterday. While I’m sure it will be cold again by the time this blog gets published, yesterday made me think about how things are changing.

In the 2017 annual HLS survey, we confirmed that wireless is the fastest growing market segment for high-level synthesis (HLS). That wasn’t much of a surprise, because…
- 21 Feb 2018
Breakfast Bytes: Is Big Brother Watching You?

Paul McLellan

I recently came across a fascinating piece by Paramal Satyal. He is Nepalese although these days he seems to live in France. His piece is largely autobiographical, but what caught my eye was a bit in the middle where he looks at one of the most ...
- 21 Feb 2018
Verification: Coming to DVCon? It's Not Too Late to Sign Up!

XTeam

Are you coming to DVCon this year? It’s right around the corner, but it’s not too late to register! DVCon is the flagship conference for all things functional design and verification, showcasing the freshest technologies, techniques, tips, and tricks.

Cadence will be in booth 702, bringing the newest tools and methodologies for working with complex silicon, SoCs, and systems. To check out the schedule, look…
- 20 Feb 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Using DDR PHY Power Features to Reduce Power Dissipation

References4U

In this week's Whiteboard Wednesday video, Marc Greenberg explains the ways to optimize power dissipation by controlling DDR PHY performance settings.

https://youtu.be/cNzggIZIhig
- 20 Feb 2018
Breakfast Bytes: embedded world 2018 Preview

Paul McLellan

It's nearly time for embedded world 2018 (yes, it likes to be trendy and put it all in lower-case), which takes place February 27 to March 1. It happens every year in Nuremberg, and is the biggest embedded conference in the world. Cadence will be the...
- 20 Feb 2018
Breakfast Bytes: Why 1 Is Not a Prime Number

Paul McLellan

It's Presidents' Day and Cadence is on holiday. So time for me to write about something that is interesting (well, it's interesting to me, anyway) but not directly anything to do with semiconductors or EDA. The Fundamental Theorem of Arithmetic Some...
- 19 Feb 2018
Breakfast Bytes: Suddenly You Are CEO. What Do You Do Next?

Paul McLellan

We've covered sales, marketing, and application engineering. Let's go up to the top, and look at what is involved in being CEO. Some aspects of the job generalize to other senior management jobs, but some aspects are unique. I do have some e...
- 16 Feb 2018
Breakfast Bytes: What's For Breakfast? Video Preview February 19th to 23rd 2018

Paul McLellan

https://youtu.be/M3p1Luf4mtk Coming from Guangzhou, China (camera Carey Guo) Monday: Why Is 1 Not a Prime Number Tuesday: embedded world Preview Wednesday: Is Big Brother Watching You? Thursday: Paul Kocher: Differential Power ...
- 15 Feb 2018
Breakfast Bytes: Zombies

Paul McLellan

What is a zombie? It depends on who you ask. Venture capitalists talk about zombies, and so do operating system programmers. Not to mention people who watch zombie movies. And in a surprise bit of news just a few weeks ago, a satellite thought to be ...
- 15 Feb 2018
Digital Design: Wondering How Moving To Advanced Nodes Might Affect Manufacturability And Yield?

Philippe Hurat

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose, CA) you can hear from experts in the field on how these challenges are being addressed. On Feb. 28 you can hear from AMD and Cadence on “Applying mac...
- 14 Feb 2018
Analog/Custom Design: Virtuoso Video Diary: Self-Paced Learning through Training Bytes

Uma Peethambaran

Cadence Education Services offers several online training courses and training bytes addressing specific features of Virtuoso products. This blog gives you a brief overview about how to find them and enroll.
- 14 Feb 2018
Academic Network: 3rd Tensilica Day in Hanover: Extending our Senses

Anton Klotz

Two events in a row are a coincidence, three events are a series. With these words Professor Holger Blume has opened the 3rd Tensilica Day at IMS Institute in Hannover and greeted more than 80 attendees, which made it the largest Tensilica-dedicated ...
- 14 Feb 2018
Breakfast Bytes: What Happens in a Patent Lawsuit?

Paul McLellan

One of the presentations in the exhibit hall, at the Chiphead Theater, was What Happens in a Patent Lawsuit? which was presented by John Strawn and Tom Millikan. I have written about patents a couple of times on Breakfast Bytes, in Patents and Standa...
- 14 Feb 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Can You Really Reduce DDR Power Dissipation by Reducing the Frequency?

References4U

In this week's Whiteboard Wednesday, Marc Greenberg examines the non-linear relationship between frequency and power consumption and the power implications of fast burst transmission vs. slow continuous transmission of data.

https://youtu.be/352-djuLWA8
- 13 Feb 2018
The India Circuit: Rural India: Technology to the Rescue?

Madhavi Rao

Last week I wrote about how mobile internet is expected to bring millions of Indians into the digital fold. Not surprisingly, there has been a spurt of tech startups focusing on the huge rural market of some 270 million, of whom about 200 million dep...
- 13 Feb 2018
Breakfast Bytes: 9½ Years to Pluto, No Go-Arounds

Paul McLellan

Here's the scene. You are Alice Bowman, who in 2018 will give a keynote at DesignCon. But that is years in the future. Today, it is 2pm on July 4, 2015. However, you don't get to eat grilled meat and drink beer since you are in the mission op...
- 13 Feb 2018
SoC and IP: See You in Barcelona at MWC!

PaulaJones

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never fails to amaze me. This year’s theme is “Creating a Better Future” and I can’t think of a better theme for Cadence – our Tensili...
- 12 Feb 2018
Breakfast Bytes: Advanced Packaging Needs Advanced Tools

Paul McLellan

At the recent DesignCon, Cadence's John Park presented Advanced Packaging Trends and Their Impact on EDA Tools. John admitted that there were too many trends to cover so he would focus on some key areas...which, not coincidentally, are also areas whe...
- 12 Feb 2018
SoC and IP: What I Learned About System Design Enablement at DesignCon

tomhackett

While attending the recent DesignCon show for the first time, I was struck by the many displays of cables, connectors, boards, and various kinds of test equipment (you can read about the impact this had on me in my previous post, A Walk Through DesignCon Turns Into a Long Journey). There was so much hardware, in fact, that I felt like I was walking through a giant Fry’s store. The impression was so strong that my first…
- 9 Feb 2018
SoC and IP: A Walk Through DesignCon Turns Into a Long Journey

tomhackett

Have you ever attended the DesignCon show? I attended the recent event for the first time and was surprised by what I saw: tons of high-bandwidth coax cables, circuit boards, connectors, and other hardware—all harnessed to very expensive scopes and channel analyzers displaying perfect eye diagrams. This was definitely a show for hardware engineers.

Walking around the show floor brought on an unexpected feeling…
- 9 Feb 2018

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