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At the Linley IoT conference recently, one of the presentations was by Steve Singer of Inside Secure. As many of the other presenters emphasized during the day, security is one of the biggest issues in IoT, above lack of standards, ease of user-setup...

In this week's Whiteboard Wednesdays video, Alex Passi explains the advantages provided by the new MIPI I3C interface. With I3C, mobile device sensors can transmit data faster, with lower power and simpler routing than with existing interfaces.

https://youtu.be/K8LjIEC3UEo

The 21^st European Test Symposium (IEEE EST) took place in Amsterdam (Netherlands) from May 23^rd-27^th. With all the ideas and challenges in designing applications and with new trends in the area of electronic-based circuits and system testing, it was good to focus on some of the other important topics of achieving system success and a future-proofed design. And Cadence had the SerDes experience to share.

The presentation…

The Cadence Academic Network is the proud sponsor of all student activities and scholarships at DAC this year. Please join us at one or all of the following events:

A. Richard Newton Young Student Fellow Program
Sunday, June 5, 7:30am to 9:00am in Room...

Virtuoso Video Diary is envisaged to be an online journal that will relay information about Virtuoso videos that are available in the Cadence Online Support Video Library. For IC6.1.7 and ICADV12.2, over 100 videos on a wide variety of new and exciting Virtuoso features have already been created. Virtuoso Video Diary brings you direct links to these videos and other related material, on a regular basis, in your mailbox…

As in previous years, a highlight of the Cadence booth at DAC is the theater, where customers and partners (plus the occasional Cadence person) present their experiences with Cadence tools and IP. Presentations take place every half hour (on the hour...

With highly effective DDR4 and LPDDR4 class memories, it’s not always easy to know what kind of memory will best fit the needs of your application? What is the optimal compromise between keeping costs in check and optimizing performance?

To answer that we have to take a step back and look at the history of the DDRs. In the PC memory area, we have the DDR2, DDR3 and DDR4. On the LPDDR front there are LPDDR2, LPDDR3…

This is the 150th blog post here at Breakfast Bytes since I arrived at Cadence in early October. Since you are reading this, however you got here, then you already know Breakfast Bytes is a blog on the Cadence website. I cover a wide range of topics affecting...

You have probably at least heard of 3D Xpoint. This is a memory technology jointly developed between Intel and Micron. I attended one of the keynotes at the Open Server Summit by Rob Peglar of Micron. He went for one of the less catchy titles of the day...

With the Allegro Design Workbench (ADW) 16.6-2015 release, you’ll have several new capabilities that enhance your productivity.

Read on for more details …

ADW Server Error Logging and Notification

The ADW Server can log the errors, warnings, and information messages and report them through e-mails. These messages enable the administrator to monitor the health of the server, and take the necessary corrective…

At CDNLive Silicon Valley, Professor Andrew Kahng of UCSD gave a presentation titled Toward New Synergies Between Academic Research and Commercial EDA. The paper won the best paper award for the academic track.

Andrew started off by pointing out that...

Design&Reuse events are always exciting for their draw of an IP-centric audience. This year’s event was held in Bangalore, on April 6^th, and drew over 130 attendees. Experienced IP providers, fables IC vendors, external IP managers, internal reuse managers, foundries IP portfolio managers, IP market analysts, IP standard gurus. The scope of event is impressive, as represented by the breadth of presented concepts…

"Simulation Acceleration” or “Accelerated Verification”  are terms commonly used to describe  a verification environment in which the Device Under Test is synthesized and runs on the emulator, while the testbench runs on the simulator. This blog describes a technique for maximizing the performance of the simulator and thus increasing the overall performance of the Simulation Acceleration.

In Simulation…

In this week's Whiteboard Wednesdays video, Ofer Steinberg explains how accelerated VIP can dramatically speed up verification and describes a method to simplify the application of a SystemVerilog UVM test environment to simulation-acceleration with the Palladium XP platform.

www.youtube.com/watch

At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence reported on what it took to pull together a version of Innovus Implementation System and a version of the ARM physical library that would work cleanly at 10nm. They titled...

I talked to Uri Tal last week, who has just joined Cadence as a result of the Rocketick acquisition. Prior to the acquisition, he was Rocketick's CEO. He gave me a little history. Rocketick started development eight years ago. They have a product called...

Mike Demler gave the keynote at the Linley IoT conference a couple of weeks ago. He is a senior analyst there, and also a senior editor of Microprocessor Report and Mobile Chip Report. His background is in analog and mixed-signal design at companies like...

Every DAC, Heart of Technology (HOT) organizes an event. This year it will be held on Monday, June 6, from 7:30pm to 11:30pm at the Speakeasy (412 Congress Avenue). This year's event will be benefiting CASA of Travis County. Sponsors will have access...

As everyone in EDA knows, Denali threw a party at every DAC for what seems like forever. It is actually since 1999 which, in EDA years, is pretty much the same as forever. When Cadence acquired Denali in 2010, the first question everyone had was not ...

In this week's Whiteboard Wednesdays video, Liron Stoler describes how the Cadence Verification IP (VIP) modular architecture provides important benefits to users in block and system-level verification.

https://youtu.be/QZwPGmM9cBI

At CDNLive in Munich, Amjad Qureshi talked about High-Speed DDR and LPDDR Memory Sub-system Challenges. Amjad is Cadence's VP of R&D for memory interface IP, so he and his team have to live with these challenges every day.

Amjad started off...

Hello Spectre RF Users,

Next week is my all time favorite technical conference - the International Microwave Symposium IMS2016, May 22-27 in San Francisco, CA at the Moscone Center.

If you're at the conference, please stop by the Cadence booth and say...

Many of the security breaches that you read about are the results of software failures such as buffer overflow. But hardware is also vulnerable to attack. After Chris Eagle's keynote, the rest of the second day at EDPS was taken up with Jasper van...

A few weeks ago, Nest announced that it was shutting down Revolv. You probably don't have a Revolv product, a sort of smart-home hub. It contains seven radios and so speaks almost any protocol of any device you might have. It cost about $300. Nest acquired...

ADAS changes everything about automotive and requires a whole new range of skills in the automotive ecosystem that they have not had before: video and image processing, deep learning, high-bandwidth networking. One area that I hadn't really thought through...