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For the first time at CDNLive Silicon Valley, Cadence Academic Network hosted an Academic Track where seven professors from leading North American universities shared their outstanding work in research and education with the attendees. The Academic Track...

Last Saturday there was a gala event at the Computer History Museum in Mountain View, where this year's fellows were inducted. Cadence had a table since one of the new fellows was Phil Moorby, the inventor of Verilog and Cadence's own first fellow. So...

Anaheim Convention Center (CA) was the center of a spectacle of technology that continues to impact our daily lives, culminating decades of innovation in communications computer imaging. There were 580 exhibiting companies, accompanied by more than 1,160 peer-reviewed papers and more than 13,000 attendees. This years’ edition of Optical Fiber Conference (OFC), the largest optical communications and networking conference…

Normally the Stanford VLAB meets in Menlo Park, but occasionally they make a foray up to the city, as they did last Thursday for a session with Ann Winblad, who was, I believe, the first female venture capitalist. The location of the meeting was kept...

In this week's Whiteboard Wednesdays video, Chris Rowen looks at the future of neural networks and the key emerging trends.

https://youtu.be/0aGA71_DBSU

There are only a few end markets for semiconductors that really drive the technology. Mobile, obviously. But mobile also drives cloud datacenter deployment since our smartphones increasingly split their functionality with big datacenters (the iPhone's...

A “scoreboard” is a verification component that checks the data sent to the DUT against the data received from the DUT. The fundamental flow of the scoreboard is simple:

• Items sent to the DUT are added to the scoreboard and stored in its data base.
• Items returned from the DUT (and collected by the monitors) are added to the scoreboard to be matched against the items sent. 

Basically, the matching algorithm…

At the recent TSMC Technology Symposium, Cadence and Mellanox demonstrated multi-lane interoperability between Mellanox’s physical interface (PHY) IP for PCIe 4.0 technology and Cadence’s 16Gbps multi-link and multi-protocol PHY IP implemented in TSMC...

Yesterday I covered the first half of the CASPA meeting last Saturday about memory in China. That was the big picture.

Simon Yang, XMC

The meeting actually opened with Simon Yang, the CEO of XMC, giving a little bit of history. But the bulk of the...

The notion of signoff has many layers to it, both in terms of complexity but also in terms of meaning. In my last blog post, I talked about some of the imprecise attributes of functional verification, like how much functional coverage you should use on a particular design. I promised to next talk about signoff, so here it is.

There are two fundamental steps most users apply to sign-off a new design, a functional milestone…

I can't keep away from work. Saturday found me in the Cadence auditorium for the quarterly meeting of CASPA, the Chinese-American Semiconductor Professionals Association. Yes, I have noticed that I am not Chinese, but I once stepped in at the last minute...

Cadence's tools Genus, Innovus, and Tempus have a lot of functionality in common. For example, they all contain the same timing engine, and a database, and constraints. One thing that they don't have is a common user interface (UI). This is due to their...

In this week's Whiteboard Wednesdays video, Arindam Guha discusses the common infrastructure between Verification IP and Accelerated Verification IP and how it assists in making the migration between simulation and acceleration seamless.

https://youtu.be/HBVZ4vWd0MA

Rain or snow does not stop our Cadence employees from being the perfect brand ambassadors. Check out the picture below!

From early January to late February, Cadence attended 14 career fairs across the country in an attempt to create brand awareness about...

The 16.6-2015 RF PCB release contains many new features and updates. Read on for more details …

Allegro Discrete Library to ADS Translator Enhancements

This release includes several enhancements in Allegro Discrete Library to ADS translator. The following image illustrates the latest UI of the tool:


Support for Schematic Symbol Version
You can now define versions for a schematic symbols in the CSV file. On loading…

Steve Mollenkopf, the CEO of Qualcomm Incorporated, gave one of the keynotes at CDNLive here in Silicon Valley. Just a little background in case you know little about Qualcomm. They started in satellite communications. Then they pioneered CDMA technology...

In many companies, there is a well-defined flow for handling monitored data items: match the input data to output data (or, match a response to a request), update data, for example latency or the time from request to response, print formatted messages, and so on.

One of the tools used by verification leaders to implement such company methodology and, at the same time, “pave the way” for variations in the flow is the…

I had lunch with Jim last week to get a little color on the early days of the Virtuoso platform. As you probably know, those days were 25 years ago, as this year is the 25th anniversary of the Virtuoso environment.

But Jim went back even further. As...

On March 17^th in the Exhibition Theatre at DATE, there was the first public announcement of the worldwide MEMS Design Contest. The organizers Cadence, Coventor, and X-FAB provided an overview of the rules of the Design Contest and the proposed MEMS-Mixed...

At this year's CDNLive, AdaptIP presented their experiences with high-level synthesis (HLS), in particular Cadence's Stratus HLS product. The presenter was billed as being Farhad Mighani but he couldn't make it, so instead it was Mike Sharp and Mike ...

At CDNLive Silicon Valley this month, Cadence announced a new family of ADE tools:  Virtuoso ADE Explorer, Assembler, Verifier and VVO (Virtuoso Variation Option).  So I'd like to start with a special section highlighting the COS content which will show you all the great new features in those tools.

Virtuoso ADE Explorer and ADE Assembler New…

Academic research often requires the learning of new concepts and techniques in a short amount of time, and the tools that you are using shouldn't be an obstacle in themselves. Rapid Adoption Kits (RAKs) are highly recommended for a quick ramp-up in the...

Tom Beckley gave the final keynote before lunch here at CDNLive in Silicon Valley. To set the scene, he told the story of watching the Space Shuttle Challenger launch in Florida where he worked for Hughes at the time. It was January 28, 1986, and as we...

I finished reading Don Dingee and Dan Nenni's book, Mobile Unleashed, the Origin and Evolution of ARM Processors in Our Devices. I guess by way of disclosure I should say that Don and Dan both blogged with me on SemiWiki for several years before I...

In this week's Whiteboard Wednesdays video, Jacek Duda describes the relationships between USB Type-C, USB 3.1, and Power Delivery specificationss, and gives examples of applications for each.

https://youtu.be/ZX--iVohGW4