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This is the first weekly video "What's for Breakfast?" that previews the blog entries coming up the following week on Breakfast Bytes.

https://youtu.be/k6soQQyx-xE

Monday: RISC-V and Chisel. RISC-V is an important new instruction set...

Cadence was shut down for the week of July 4th, so I went to Japan with a friend who had never been before. Despite having been two or three dozen times before in my life, this was actually my first time in Japan as a tourist. I've had the occasional...

At the recent GSA Silicon Summit at the Computer History Museum in Mountain View, CA, the keynote was given by Wally Rhines on consolidation in the semiconductor industry, titled "Merger Mania." He started off by pointing out that the number of recent...

Chipworks buys hundreds of devices every year and strips them down to look at the silicon that is in them. In some cases, they go much further, decap the chips, and work their way down the layers so that they know which process it is in, how many tracks...

In this week's Whiteboard Wednesdays video, Chris Rowen describes how to use processor clusters to implement neural networks. This approach allows you to achieve higher frame rates, which leads to increased accuracy while processing large amounts of data and accurately analyzing the results.

www.youtube.com/watch

Flash memory is being utilized in computers and electronic devices found in Automotive, IoT, Drones, Connected Home, and other emerging applications, demanding ever higher transfer rates and lower latency. Expanding the flash Serial Peripheral Interface (SPI) accesses to 8 I/Os (hence Octal SPI) increases the Serial NOR Flash throughput and provide a more efficient solution for emerging applications, while providing backwards…

If you design with flash memory components or IP solutions, head on over to the Santa Clara Convention Center to attend the Flash Memory Summit that is being held August 9-11 in Santa Clara, California.

Cadence recently announced a partnership with Micron to support Micron’s high-performance, low pin count XTRMFlash interface as part of its controller IP portfolio. This new and faster NOR flash is going to revolutionize…

Last week was the Linley Mobile Conference, although it is now the Mobile and Wearables Conference. As always, Linley Gwenap gave the opening keynote with his overview of the industry. One milestone that coincidentally was announced is that Tim Cook,...

Scaled-sigma sampling (SSS) is an efficient algorithm to solve the high-yield estimation problem, which happens when your circuit needs to have a really low failure rate, like one in a million or one in a billion. This can be because you are designing a highly repetitive circuit like a memory cell or flip-flop, or you are an automotive or medical designer who just wants to be very…

The new Virtuoso ADE product suite is packaged with a lot of easy-to-use, productivity-enhancing, and robust features including a new set of SKILL functions that make it easy to write and deploy efficient regression scripts.The new functions can be used with both Virtuoso ADE Explorer and Virtuoso ADE Assembler, and provide ease and efficiency in setting up regression flows from batch mode. These functions can be used only…

The full agenda for CDNLive Boston is now available. This is really "East Coast" CDNLive since it is the only CDNLive in the US outside of Silicon Valley. I've not been before, but I understand that people from places like Atlanta and Florida attend,...

If you live in the US, then it is hard to believe how dominant Nokia was in mobile. For a time, one in every three mobile phones sold was a Nokia. But they were never a major force in the US for various reasons. But they built a million phones a day back...

New Model Management capabilities are now available in the SPB 16.6 Allegro Design Workbench (ADW) release.

The new model management capability involves creating an environment that manages new model types for the PCB Librarian and other model editors. The benefits:

• Enhance the 16.6 SI DM Model flow for ease of use
• Create a new generic adapter to support a file system based model type
• Create a new generic model…

When using the Add Connect command in the 16.6 Allegro PCB Editor, the active layer field will now automatically synchronize to that of a single visible layer. Previously, any visibility adjustment to limit the display to a single etch layer would typically require an additional adjustment to the active layer setting.

Invoke the ‘Add Connect’ command. Disable the visibility of all etch layers:

Enable the…

By default, the top and bottom stackup layers do not support the placement of embedded components. When an attempt is made to change ‘Embedded Status’ to either ‘Body up’ or ‘Body down’, the system will prompt you accordingly. To help facilitate the requirement for placing components between the top and bottom layers, the 16.6 Allegro PCB Editor release now supports the placing of components…

Applying a weighting factor to a Noise Summary run requires lots of steps and the results cannot be evaluated without using the form. Wouldn't it be much easier if you could have a calculator function to do this?

You can create a custom function in the calculator that uses the script attached, weightedTotalNoise.il, simplifying this flow.

In order to apply a weighting factor to a Noise Summary…

Hey, did you hear the buzz around the new Virtuoso ADE product suite, which was introduced in IC6.1.7? The products in this suite—Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier—have made a good start, just as we expected!

The new single-test simulation environment, Virtuoso ADE Explorer, provides some really exciting features. Our favorite ones are real-time tuning with Spectre,…

For nearly all applications, customers continue to demand smaller, lighter, and more cost-effective products. Competitive pressures also force designers to bring these new products to market at an ever-increasing rate. Designers can deploy flexible PCB materials (flex/rigid-flex) to meet challenging form-factor requirements, eliminate connectors, and improve performance.

It might seem a bit premature to be talking about IEDM since it isn't until December. But the deadline for submissions has been extended this year to August 10 (so still just a couple of weeks away). Why? As this year's publicity chair, Martin Giles,...

Today at the Linley Mobile and Wearables Conference in Santa Clara, Cadence is announcing the latest Tensilica DSP. The Tensilica^® Fusion G3 is a multi-purpose low-power DSP targeted at mobile and other markets. Usually when we design a new processor...

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In this week's Whiteboard Wednesdays video, Paul Garden provides an introduction to the new Tensilica Fusion G3 DSP for automotive, mobile, industrial, and general embedded DSP applications. He’ll discuss the main features of the Fusion G3 DSP, highlight some of the target applications, and provide a quick overview of some of the key software deliverables. The Fusion G3 is a multi-purpose fixed- and floating-point DSP…

One of the most interesting sessions that I attended at SEMICON West the week before last was titled Pathfinding Beyond 5nm. This was moderated by David Hemker, the CTO of Lam Research.

An Steegen, imec

The first speaker was An Steegen of imec. She...

CDNLive India is coming up on August 9th and 10th in Bengaluru. I will be there and so Breakfast Bytes will be covering some of what goes on there. It is not my first trip to India or even to Bengaluru (although it was still called Bangalore back then...

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