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Over the years I've often hoped to have the ability to show someone (a customer, or one of our field engineers) a bit of e code, and explain what it actually does. People say that a picture speaks more than a 1,000 words, so you could say a bit of code does have the same effect on engineers.

Well, since the beginning of this week you can do exactly that with your e code on a very neat website called http://www.edaplayground…

In my previous blog post, I wrote how much better than the existing Type-A and Type-B plugs the recently announced Type-C connector will be. Actually, the Type-C connector is only a part of the equation of how better the USB ecosystem will become when all USB specifications announced this year find their places in future devices. The others are USB 3.1, with its up to 10Gbps data rate, Power Delivery 2.0, and Alternate…

Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it.

As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the digital…

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends in today's consumer market. He deep dives into the comparison between LPDDR4 and DDR4 DRAM.

http://youtu.be/pxuixROtlPI

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation criteria when purchasing a DDR PHY IP solution. Kishore details topics such as power, performance, and area (PPA), interoperability, DFI, and floorplan flexibilty.

www.youtube.com/watch

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase.

Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics test…

The 16.6 Allegro PCB Editor release contains two new selection options, lasso and path, which are available with commands that normally support temp groups; ‘Move’ and ‘Highlight’ are two examples of those commands.  If working in an application mode, you can access these selection options from the RMB – Selection Set menu:
       
                

Read on for more details …

Let’s look at a few examples that…

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the interface specification.

http://youtu.be/NZyFL4TbeME

Recently, an article was published in Printed Circuit Design and Fab about Multi-Fabric Planning for Efficient PCB Design (see page 22 of printed magazine).

Today's BGA-style packages have a significant impact on PCB layer count, route complexity, and cost. Efficient BGA net assignment and patterning of power and ground pins can make the difference between a four- and a six-layer PCB. Historically, there's been minimal…

There has been a flurry of activity on COS over that past couple of months. I can't even come close to listing everything, but here are some of the highlights. Be sure to check out the "Training Bytes" section at the end of this post for information on a recent initiative in which Cadence training experts are publishing short video excerpts from our most popular classes.

0. Many of the product…

I attended the Gartner Semiconductor briefing on Oct. 23, 2014, the theme of which was “The Internet of Things: Use Cases that Move Beyond the Hype.” Most attendees were from the semiconductor industry, of course.

Huge numbers like the following were thrown out:

• In 2020, 8+ billion things shipped in one year.
• This will generate 35 billion semiconductor devices requiring 6 million wafers in 2020.

One…

Key Findings:  Nearly 100% of SoCs are mixed-signal to some extent.  Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but the modeling step is the biggest hurdle to overcome.  Without the magical models, the process breaks down for lack of performance, or holes in the chip verification.

In the last installment of The Low Road, we were at the…

In this week's Whiteboard Wednesdays video, Tom Hackett talks about Cadence Verification IP (VIP) productivity tools in the VIP catalog. These tools, PureView and TripleCheck, help engineers better match their VIP to their design under test ensuring better verified designs.

http://youtu.be/MXRZGulFRKo

Isn’t it interesting how, with time, all the nitty-gritty of technology is starting to get more and more attention? Is it because we’re getting smarter, or is it that everything is so much the same on the surface that the differentiation needs to be found deep inside, where no one looked for it before?

I think it’s both, especially for such a well-known technology as USB. I mean, who doesn’t know it? We use…

This post concludes the series of blog posts that discuss the dynamic capabilities of the Reflection API in e. Part one described the basics of generic value assignments and retrievals, using untyped and value holders. Part Two explained how to manipulate field values and invoke methods in a generic manner. If you have not read those two blogs and are not familiar with those concepts yet, I strongly recommend reading them…

The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture) package features the ability to transfer objects from one verification framework to another via multi-language TLM ports. Check out Appendix A if you are a first-time user of UVM-ML OA.

This feature makes many things possible, such as:  

• Sequence layering where one framework generates the sequence item and the other drives it to…

Field access and method invocations

In the previous blog, we explained what are untyped variables and value holders in e, and how to assign and retrieve values to/from them. In this and the next blogs, we will see how they can be used in conjunction with the Reflection API, to perform operations at run time.

Normally, when you declare fields in your e structs and units, you then procedurally assign values to those fields…

Key Findings: Many more chip programs are crossing the tipping point and need advanced mixed-signal verification methodologies and technologies. A deterministic march to closure is needed.  The Cadence party for mixed-signal verification is the hottest ticket in town.

With some important public events now behind us and more on the horizon, the agendas make it clear that there is mounting pain in the realm of verifying…

CDNLive Silicon Valley (March 10-11, 2015, Santa Clara Convention Center) provides an excellent opportunity to share your experiences and insights on key technical and industry issues. 

And it’s not just about Cadence tools.  We’re hosting a track on IP and, if we get enough papers, we'll expand this to two IP tracks.

Submit an abstract for consideration at the 2015 conference. Here’s the link with…

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan breaks down Cadence's high-performance, low-latency controller solution for PCI Express (PCIe).

http://youtu.be/lEurRUjGS2c

This week, you can view a couple of videos where customers describe how they used the Sigrity and Cadence SiP Digital Layout products to simulate, verify, and reduce the size and costs of their designs.

Ericsson Meets DDR and PCIe Specs While Avoiding Crosstalk
In this Expert Insights video from CDNLive India 2014, Sheetal Jain, a member of the modem organization at Ericsson Design, discusses how his team verified their…

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable options for Cadence 10/40G Ethernet MAC, integrated PCS, and SerDes IP.

http://youtu.be/CaQ6tPPQqA4

The 16.6 Allegro PCB Editor release contains several enhancement to the Artwork Film generation.

Read on for more details …

Film Domain

Artwork films can now be designated by the domain where they appear. There are four domains available; Artwork, PDF, IPC2581, and Visibility. Access the User Interface by clicking on ‘Domain Selection’. One of the benefits of the domain form is the ability to segregate films for…