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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Coverage Closure – A Progression Instead of Just a Destination

The testing and verification of a complex hardware or software system, such as modern…

• 2 min read
ml , coverage , bugs , simulation

Exploring World of Flash Memory: Serial, Dual, Quad, and Octal Interface

Overview In the world of digital data storage, flash memory has become an indispensable…

• 3 min read
Verification IP , DATA Storage , flash , serial flash , VIP , Memory Model Portfolio , nor flash , OSPI

Training Insights – A New Free Online Course on the Protium System for Beginner and…

The Cadence Protium System is used for prototyping. It is a hardware platform that…

• 2 min read
digital badge , online_training , protium x2 , Protium , blended_training , training bytes , live

Pre and Post-Silicon Verification Have Never Been Closer! Leveraging Portable Stimulus…

The initial focus of the Portable Test and Stimulus Standard (PSS) was pre-silicon…

• 5 min read
Perspec , post-silicon , ATE , pss , portable stimulus , verification

Low-Power IC Design: What Is Required for Verification and Debug?

Low-Power Design Techniques Are Needed In today’s world, energy saving is a hot topic…

• 6 min read
Low Power , debug , Functional Verification , UPF , VerisiumDebug

How to Maximize Productivity and Lower Cost for Enterprise Prototyping

Semiconductor chips are often produced as application-specific integrated circuits…

• 6 min read

Streamlining Your Verification Environment with Xcelium ML

When it comes to projects that involve cover groups and properties, and tests that…

• 1 min read
coverage , xcelium ml , xcelium apps

Lightelligence Accelerates DFT Simulation Using Cadence Xcelium Multi-Core

The growing design complexity of today’s system on chips can result in long hours…

• 3 min read
DFT , Lightelligence , Multi-Core , xcelium , verification

Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and Python…

The Verisium Debug platform is optimized for scalability, supporting debugging of…

• 1 min read
Verification planning and management , training , webinar , Verisium Debug

Understanding UCIe Design Verification Topologies

UCIe or Universal Chiplet Interconnect Express is the fastest growing chiplet interconnect…

• 3 min read
ucie , Verification IP , chiplet , VIP , die

Accelerating Your Overall HW/SW Verification and Validation Productivity Using Dynamic…

With the increasing complexity of system-on-chip (SoC), the associated software stack…

• 8 min read
Analog Devices. ADI , software verification , validation , protium x2 , palladium z2 , Accelerate , productivity , Hardware/software co-verification , verification

Verisium AI-Driven Verification Platform Improves Debug Productivity by 6X at Re…

With the surge in usage requirements and increasing customer demands, hardware design…

• 3 min read
featured , coverage , throughput , machine learning , Regression , simulation , verification

Training Insights – Webinar –: Solve Tricky SVA Problems with Jasper Visualize and…

Are you experienced in using SVA? It’s been around for a long time, and it’s tempting…

• 2 min read
digital badge , online , Visualize , Jasper , training , webinar , SVA , app , verification

Flex Ethernet (FlexE): Unlocking the Physical Bandwidth Constraints

Efficient and flexible use of bandwidth is the key to optimizing traffic flow for…

• 3 min read
Verification IP , 5G Network , Ethernet VIP , Functional Verification , FlexE , VIP , Flex Ethernet , Ethernet , Hyperscalers , data centers , OIF , verification

What Makes a Next-Generation Debug Solution?

For the past few decades, design and verification technology have made great progress…

• 5 min read
Functional Verification , debugging tips , debugging

Improve Regression Throughput and Find Bugs at Pace

Scaling chip size and increasing functionality over SoCs has increased complexity…

• 4 min read
xcelium simulator , Xcelium ML A

Automating Data Coherency and Performance Testing of High-Speed SoCs with CXL In…

2023 is here, and technology trends around Compute Express Link (CXL) and the next…

• 2 min read

USB3 Gen T Tunneling Over USB4

USB Promoter Group recently released USB4 Version 2.0 and this updated specification…

• 2 min read

DDR5 DIMM Design and Verification Considerations

DDR5 is the latest generation of the DDR server memory capable of supporting data…

• 4 min read
Verification IP , ddr5 , DDR5 DIMM , VIP , JEDEC , LRDIMM , DRAM , RDIMM , memory models , PCDDR , verification

UCIe: Enabling the Chiplet-Based Ecosystem

Universal Chiplet Interconnect Express (UCIe) is a novel specification that defines…

• 2 min read
ucie , Verification IP , chiplets , System Design and Verification , VIP

Introduction to Embedded DisplayPort (eDP) version 1.5

Embedded DisplayPort 1.5 (eDP 1.5) is an interface standard that is based on the…

• 1 min read
Verification IP , Functional Verification , DisplayPort , VESA , EDP

Training Insights – VHDL Language and Application

Cadence has released a new online VHDL training course free for Cadence Customers…

• 2 min read

Demonstrating PCIe 6.0 Equalization Procedure

The Link equalization procedure enables components to adjust the Transmitter and…

• 4 min read

SD Host Controller for SD Card Verification

SD Host Controller was introduced to transfer data to SD Card from system memory…

• 2 min read
Verification IP , host , Memory , VIP , SD

Training Insights - Brand New Free Online Course on Perspec System Verifier for Beginner…

Cadence® Perspec System Verifier is a portable stimulus, system-on-chip (SoC) verification…

• 3 min read
Verification planning and management , verification strategy , Perspec , perspec system verifier , verification management , Verification Acceleration , System Verification , verification coverage , verification

Understanding Latency versus Throughput

One of the effects of adopting a High Level Synthesis design methodology is that…

• 2 min read
High-Level Synthesis , throughput , ESL High Level Synthesis , Team ESL , latency , ESL

Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and Py…

Join Cadence Training and Principal Application Engineer Daniel Bayer for this free…

• 1 min read
Verification planning and management , Verisium Debug , verification

How to Verify Complex PIPE Interface Based PHY Designs?

High-end SOC architectures today requiring more area and higher speed to transfer…

• 2 min read
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