Signal and Power Integrity (PCB/IC Packaging) Blogs

The 2019 HF4 production release for Clarity, Celsius, and Sigrity tools is now available for download at  Cadence Downloads .

Signal integrity (SI) engineers tasked with successfully implementing memory interfaces, such as DDR4 and DDR5, face major challenges in meeting the requirements in a timely fashion. The traditional design workflow typically assumes an ideal power d...

The 2019 HF2 production release for Clarity, Celsius, and Sigrity tools is now available for download at Cadence Downloads. SIGRITY2019 HF2 For information about supported platforms, compatibility with other Cadence tools, and details of key...

Designing an optimized power supply and a PCB without board-level SI/PI problems on time requires a tight collaboration between the design, layout, and PI engineers through an integrated design platform. A team-oriented design flow will empower the ...

Figure 1: High-performance PCIe-based graphics card There is a trend in the data center industry moving toward heterogeneous computing in order to satisfy workloads that are computationally intensive. These trends are driving the development of soft...

In the beginning of our universe, enormous amount of heat or energy was generated and released during the period of 0 to 10-43 sec, in theory while backed up by models and measurements, about 13.8 billion years ago. Since then, a variety of phy...

The 2019 HF1 production release for Clarity, Celsius, and Sigrity Tools is now available for download at Cadence Downloads . SIGRITY2019 HF1 For information about supported platforms, compatibility with other Cadence tools, and details of key issu...

A multi-CPU architecture running on both cloud and on-premise computers can better optimize large 3D structures in ICs, packages, and PCBs serving high-speed signaling designs.

The Sigrity 2019 production release is now available for download.

Accurate 3D EM simulation is increasingly necessary as data rates increase. For example, last year Cadence announced IP for 112G long-reach SerDes . The IP lives on a 7nm chip, which is a reasonably well-controlled environment. But think what the sig...

With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 di...

As transistor device scaling gets closer and closer to physical limits, more and more companies have been looking beyond silicon and into multi-die approaches with advanced packaging to keep the innovation and speed performance trend going forward i...

In modern electronic systems, there may be tens to hundreds of DC rail voltages used in the system, with voltage levels, for example, ranging from 48V/24V to 3.3V, 1.8V, 1.2V and even as low as 0.8V. Usually these systems will have a few input ...

Gaining an understanding of power plane loop inductance is important for efficient printed circuit board (PCB) designs. Unfortunately, board designers too often use inappropriate rules of thumb when laying out the power delivery network (PDN) ...

Cadence will kick off this year’s CDNLive worldwide user conference series starting with Silicon Valley on April 2-3 at the Santa Clara Convention Center in Santa Clara, California. The keynote presentations begin at 10:30 a.m. and will includ...

It is no secret that serial link data rates have skyrocketed over the past 15 years or so. What was considered cutting edge back then in the 2.5 – 3.25 Gbps range now appears in stark contrast to the 112Gbps PAM4 technology we see today. Yet t...

System designers are familiar with standard DDR4 RAM components but with the demands on increasing performance and decreasing power consumption in mobile products, LPDDR4 and its variation, LPDDR4X, have become the desired memory devices for in-vehi...

Happy new year! We want to invite you to visit us in booth 711 on the DesignCon Expo floor. Learn about how we can address your design challenges with Cadence® Sigrity signal integrity and power integrity tools, multi-gigabit SerDes...

A new paradigm shift is now happening in the electronics industry with systems design. The conventional thinking of designing an electronic system with a single monolithic SoC is changing to using a multi-die approach with chiplets and advance...

2018 is going to be remembered as the year of 3D for Sigrity. As part of Cadence’s Sigrity 2018 release , we introduced the new Sigrity 3D Workbench technology included as part of the Sigrity PowerSI® 3D EM Extraction Option...

In part 3 of this series, we used the concept of thermal resistors to develop a thermal equivalent network of a system and determined its equivalent junction to ambient thermal resistance. With this approach, we were able to link thermal resis...

In part 2 of this blog series we looked at the three different modes of heat transfer and related them to equivalent thermal resistances. In this blog, we’ll use the concept of thermal resistors to develop a thermal equivalent network of...

In part 1 of this blog series we discussed the duality between the electrical and thermal conduction domains. In this blog, we’ll take a look at the three different modes of heat flow or heat transfer and relate these to thermal resistan...

This year’s CDNLive Silicon Valley user conference had more than 100 presentations from 12 different technical tracks. More than 20 exhibitors participated in the Designer Expo. The customer paper on system-level PDN analysis methodology f...

Have you ever had a product exceed temperature specifications and wondered what you, as an electrical engineer, can do to solve or mitigate thermal issues in your product? As an electrical engineer in today’s world of electronics, we are...