Cadence Community

How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI

By Sigrity | 23 May 2019

With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 di...

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Serial link analysis | ami builder | equalization | PAM-4 | IBIS-AMI | DesignCon 2019 | SerDes | Sigrity | SystemSI
Finally, A Certified and Correlated Reference Flow for Advanced Package Designs

By Sigrity | 9 May 2019

As transistor device scaling gets closer and closer to physical limits, more and more companies have been looking beyond silicon and into multi-die approaches with advanced packaging to keep the innovation and speed performance trend going forward i...

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advance packaging | Silicon-interposer 2.5D package-based test | reference flow | Samsung | CDNLive 2019 | package design | DesignCon 2019 | FO-PLP | Sigrity | CDNLive San Jose | Package signoff | Advanced Package design and sign-off reference flow
How to Accelerate Your Thermal Aware PI Design?

By Sigrity | 25 Apr 2019

In modern electronic systems, there may be tens to hundreds of DC rail voltages used in the system, with voltage levels, for example, ranging from 48V/24V to 3.3V, 1.8V, 1.2V and even as low as 0.8V. Usually these systems will have a few input ...

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PCB | DC | PI | DesignCon | PDN | power integrity | OptimizePI | DesignCon 2019 | PowerTree | electrical-thermal co-simulation | Sigrity | thermal | PowerDC
Power Plane Loop Inductance Guidance for PDN Designers

By Sigrity | 11 Apr 2019

Gaining an understanding of power plane loop inductance is important for efficient printed circuit board (PCB) designs. Unfortunately, board designers too often use inappropriate rules of thumb when laying out the power delivery network (PDN) ...

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SI | DesignCon | PDN | Power plane loop inductance | DesignCon 2019 | signal integrity | Sigrity | PowerSI
Join us at CDNLive Silicon Valley 2019

By Sigrity | 27 Mar 2019

Cadence will kick off this year’s CDNLive worldwide user conference series starting with Silicon Valley on April 2-3 at the Santa Clara Convention Center in Santa Clara, California. The keynote presentations begin at 10:30 a.m. and will includ...

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CDNLive | CDNLive 2019 | CDNLive San Jose
Exposing Adaptive EQ in 32 Gbps Receivers

By Sigrity | 21 Mar 2019

It is no secret that serial link data rates have skyrocketed over the past 15 years or so. What was considered cutting edge back then in the 2.5 – 3.25 Gbps range now appears in stark contrast to the 112Gbps PAM4 technology we see today. Yet t...

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dfe | SI | FFE | DesignCon | Adaptive Equalization | AGC | IBIS-AMI | EQ | DesignCon 2019 | signal integrity | SerDes | Sigrity | SystemSI | Automatic Gain Control
Simulation of LPDDR4X Interface: What Designers Need to Know and Do

By Sigrity | 21 Feb 2019

System designers are familiar with standard DDR4 RAM components but with the demands on increasing performance and decreasing power consumption in mobile products, LPDDR4 and its variation, LPDDR4X, have become the desired memory devices for in-vehi...

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Serial link analysis | SI | LPDDR4 | DesignCon | DesignCon 2019 | signal integrity | Channel simulation | Sigrity | BER | SystemSI
Cadence Sigrity at DesignCon 2019

By Sigrity | 17 Jan 2019

Happy new year! We want to invite you to visit us in booth 711 on the DesignCon Expo floor. Learn about how we can address your design challenges with Cadence® Sigrity signal integrity and power integrity tools, multi-gigabit SerDes...

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SI | PI | electronics/photonic design automation | DesignCon | Multi-Gigabit | Advanced IC packaging | power integrity | IC package design | IBIS-AMI | DesignCon 2019 | signal integrity | SerDes | DDR | Sigrity
Chiplets -- Reinventing Systems Design

By Sigrity | 29 Nov 2018

A new paradigm shift is now happening in the electronics industry with systems design. The conventional thinking of designing an electronic system with a single monolithic SoC is changing to using a multi-die approach with chiplets and advance...

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SI | PI | chiplets | multi-die approach | chiplet-based systems | power integrity | IC package design | systems design | signal integrity | interposer extraction | Sigrity | heterogenous integration | advanced packaging technology
New Sigrity 3D Workbench Used in Designing and Optimizing Next Generation High-Speed Connectors

By Sigrity | 8 Sep 2018

2018 is going to be remembered as the year of 3D for Sigrity. As part of Cadence’s Sigrity 2018 release , we introduced the new Sigrity 3D Workbench technology included as part of the Sigrity PowerSI® 3D EM Extraction Option...

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Sigrity 2018 release | 3D Workbench | Mechanical Structures | CDNLive | High Speed Structure Optimization | PowerSI 3D EM Extraction Option | 3DEM | 3D | Sigrity | High Speed design
EE Thermal 101 – Thermal basics for Electrical Engineers (Part 4 of 4)

By Sigrity | 24 Aug 2018

In part 3 of this series, we used the concept of thermal resistors to develop a thermal equivalent network of a system and determined its equivalent junction to ambient thermal resistance. With this approach, we were able to link thermal resis...

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EE Thermal | temperature | Thermal Basics | Heat transfer | PowerDC
EE Thermal 101 – Thermal Basics for Electrical Engineers (Part 3 of 4)

By Sigrity | 9 Aug 2018

In part 2 of this blog series we looked at the three different modes of heat transfer and related them to equivalent thermal resistances. In this blog, we’ll use the concept of thermal resistors to develop a thermal equivalent network of...

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EE Thermal | temperature | Thermal Basics | Heat transfer | PowerDC
EE Thermal 101 – Thermal Basics for Electrical Engineers (Part 2 of 4)

By Sigrity | 25 Jul 2018

In part 1 of this blog series we discussed the duality between the electrical and thermal conduction domains. In this blog, we’ll take a look at the three different modes of heat flow or heat transfer and relate these to thermal resistan...

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EE Thermal | temperature | Thermal Basics | Heat transfer | PowerDC
Cadence Sigrity OptimizePI Technology Highlighted at CDNLive SV 2018

By Sigrity | 13 Jul 2018

This year’s CDNLive Silicon Valley user conference had more than 100 presentations from 12 different technical tracks. More than 20 exhibitors participated in the Designer Expo. The customer paper on system-level PDN analysis methodology f...

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PI | PCB PI | power integrity | Sigrity OptimizePI | OptimizePI | Sigrity
EE Thermal 101 – Thermal Basics for Electrical Engineers (Part 1 of 4)

By Sigrity | 12 Jul 2018

Have you ever had a product exceed temperature specifications and wondered what you, as an electrical engineer, can do to solve or mitigate thermal issues in your product? As an electrical engineer in today’s world of electronics, we are...

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EE Thermal | temperature | Thermal Basics | Heat transfer | PowerDC
What Is COM /JCOM Channel Compliance All About?

By Sigrity | 13 Jun 2018

In today’s world of double-digit gigabit-per-second data rates it is imperative that engineers properly design and characterize their system to meet standards compliance. This sounds simple enough but actually simulating a high-speed ser...

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SI | JCOM | Channel Operating Margin (COM) | COM/JCOM | JCOM channel compliance | COM | Channel Operating Margin | signal integrity | SystemSI
Designing a PCB in Harmony with Your 3D Extraction Expert

By Sigrity | 4 Jun 2018

You know who we are talking about. The guy in the corner with all the PhDs hanging in his/her office. Everyone goes to Mr/Ms. 3D-Expert to get their 3D structures analyzed. He/She knows all the bells and whistles and can make a tool...

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SI | 3D EM | High Speed Structure Optimization | 3D EM HSSO | 3D EM High Speed Structure Optimizer | signal integrity | 3D | HSSO | Sigrity | System Serial Link | Allegro
Power-Aware SI DDR4 Simulation: You Have a Choice!

By Sigrity | 10 May 2018

Simultaneous switching noise (SSN) caused by simultaneous switching outputs (SSO) has been a hot topic for decades in signal integrity (SI) circles (see figure to the right). Some claim only a SPICE simulation using transistor-level models can...

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Speed2000 | DDR4 | FDTD | power-aware | SystemSI | SSN
SI Methodology for Multi-Gigabit Serial Link Interfaces (8 of 8)

By Sigrity | 24 Apr 2018

Automated Compliance Checking With detailed post-layout interconnect in place, and the IBIS-AMI models properly executing, attention can turn to compliance checking for the specific interface of interest, which is PCI Express Gen 4 in our example. Ea...

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Serial link analysis | SI | IBIS-AMI | PCIe | signal integrity | Compliance Checking | SerDes | Sigrity
Some Don't Like It Hot: Thermal Model Exchange

By Sigrity | 28 Mar 2018

Engineers today are faced with complex as well rapid design changes that require multiple design tools to work in conjunction with others. Both the MCAD and ECAD eco-systems have addressed this with their own neutral file format such as SAT, IGES, I...

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CFD | neutral file format | electrical-thermal co-simulation | Sigrity | thermal | PowerDC
Thermal Analysis of Package/PCB Systems: Challenges and Solutions

By Sigrity | 9 Mar 2018

More and more package/PCB system designs are requiring thermal analysis. Power dissipation is a critical issue in package/PCB systems design which requires careful consideration of the thermal and electrical domains. To better understand therma...

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PCB | PI | power integrity | Voltus | electrical-thermal co-simulation | thermal | PowerDC
SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)

By Sigrity | 22 Feb 2018

Backchannel Training Another capability related to equalization adaptation is backchannel training. Many high speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide i...

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Serial link analysis | IBIS-AMI | PCIe | signal integrity | Backchannel | Sigrity
SI Methodology for Multi-Gigabit Serial Link Interfaces (6 of 8)

By Sigrity | 8 Feb 2018

Simulating with IBIS-AMI Models By this point in the process, the SerDes component suppliers should have provided any missing IBIS-AMI models, which should be updated in your simulation testbench if they exist and are available. Now the focus shifts ...

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Serial link analysis | SI | Multi-Gigabit | IBIS-AMI | PCIe | signal integrity | SerDes | Sigrity
Designing Data Bus with DDR5 Technology Today? Yes, It Is Possible!

By Sigrity | 18 Jan 2018

Many system designers have been working with DDR4 RAM components in the past couple years and using them in system designs. With product demands of increasing performance and decreasing power budget, expectations for faster memory devices neve...

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ddr5 | AMI | Memory interface | IBIS | IBIS-AMI | DDR | Sigrity
Improve High-Speed Serial Link Design with IBIS-AMI Backchannel Simulation

By Sigrity | 18 Jan 2018

As signal integrity engineers, we know adaptive equalization is used in today’s multi-gigabit serial links to combat the effects of inter-symbol interference (ISI) due to a bandlimited channel. But how are we currently simulating this, especial...

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Serial link analysis | Backchannel Simulation | IBIS-AMI | SerDes | Sigrity | SystemSI

Signal and Power Integrity (PCB/IC Packaging) Blogs