• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      CF202606104231
      CF202606104231 111 Points
    • 2
      BB202608098129
      BB202608098129 80 Points
    • 3
      Zhifeng Jin
      Zhifeng Jin 55 Points
    • 4
      Hoangkhoipcb
      Hoangkhoipcb 45 Points
    • 5
      steve
      steve 40 Points
  • Leaderboard

    • 1
      steve
      steve 17,924 Points
    • 2
      oldmouldy
      oldmouldy 13,850 Points
    • 3
      eDave
      eDave 10,386 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Not Answered

    NC Drill Holes Appear Offset from Gerber Artwork

    Category: Allegro X PCB Editor

    By Electro Node

    •

    updated 12 hours ago by avant

    1 replies • 31 views
  • Discussion

    Creating Footprints from Templates in Orcad X Presto

    Category: OrCAD X Presto PCB

    By vidhyaparameswari

    •

    started 14 hours ago

    0 replies • 10 views
  • Not Answered

    Why is include and remove option for xnet grayed out in system capture while working in schematic canvas?

    Category: Allegro X System Capture (EE Cockpit)

    By Smith ecad

    •

    started 16 hours ago

    0 replies • 24 views
  • Discussion

    Spectre: Missing nodes in the operating point report. A configuration issue or a simplification?

    Category: Mixed-Signal Design

    By AF202602026942

    •

    started 21 hours ago

    0 replies • 45 views
  • Discussion

    regarding Gatelevel simulation signals

    Category: High-Level Synthesis

    By BharathST

    •

    started 21 hours ago

    0 replies • 20 views
  • Discussion

    What is Preventing Designers from Improving Decoupling?

    Category: Allegro X PCB Editor

    By John T

    •

    updated 21 hours ago by John T

    2 replies • 129 views
  • Not Answered

    Automated Layout Validation During PCB/Package Translation in Sigrity & Clarity

    Category: Sigrity

    By cistheta07

    •

    started 1 day ago

    0 replies • 21 views
  • Discussion

    SysCap – Tip of the Week: Placing multisection part on schematic

    Category: Allegro X System Capture (EE Cockpit)

    By DesignTech

    •

    updated 3 days ago by GH202604086612

    1 replies • 3325 views
  • Not Answered

    OrCAD how to create a correct Variant report through TCL

    Category: Allegro X Scripting - TCL

    By PatEscher

    •

    updated 3 days ago by PatEscher

    3 replies • 294 views
  • Suggested Answer

    Request for Allegro Board File to ASCII Conversion Guidance

    Category: Allegro X PCB Editor

    By PK202511125928

    •

    updated 3 days ago by steve

    2 replies • 173 views
>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information